以核心電路為基礎之單晶片系統設計方法整合來自於不同來源的技術。隨著製程技術的進步與設計技巧的的提升，今日的單晶片系統將成為未來的內嵌核心電路。階層式設計架構將使得測試整合面臨新的挑戰。
　　在此我們提出一個單晶片系統的測試排程技巧，用於減少包含階層式內嵌核心電路之單晶片系統的測試時間。有別於以往的方法所假設的，在排程時將階層式設計架構打散在同一層級；我們提出的排程技巧實際考量階層式設計架構所帶來的限制。這些限制包括測試存取機制的分配、有限的輸出入針腳數目，以及階層式核心電路的功率消耗等問題。在本論文中包含針對ITC'02 SOC Test Benchmarks所產生的實驗數據。此外，我們也發展了數個應用於測試排程的自動化工具。

　　Core-based system-on-chip (SOC) design methodology integrates heterogeneous technology from multiple sources. As fabrication technology and design technique make progress, today's SOC may become tomorrow’s embedded core. The design hierarchy of the SOC results in test integration challenges.
　　We propose an SOC test scheduling technique that minimizes the test application time of the SOC with hierarchical embedded cores. Unlike previous work in this area that assumes the SOC design hierarchy to be flattened, the proposed technique takes the design hierarchy constraints into account. These constraints include TAM assignment, fixed I/O pin number, and maximum power dissipation of the hierarchical cores. Experimental results are presented for ITC'02 SOC Test Benchmarks. Tools for the automation of test scheduling process are also developed.

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