| 研究生: |
王祈翔 Wang, Chi-Hsiang |
|---|---|
| 論文名稱: |
透過整數線性規劃演算法適用於電源門控設計且能考慮電壓降之有效電源網路合成 Effective Power Network Synthesis for Power Gating Designs with IR-Drop Consideration Using Integer Linear Programming |
| 指導教授: |
林家民
Lin, Jai-Ming |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2024 |
| 畢業學年度: | 113 |
| 語文別: | 英文 |
| 論文頁數: | 41 |
| 中文關鍵詞: | 電壓降 、電源網路合成 、整數線性規劃 、電源門控設計 |
| 外文關鍵詞: | IR-drop, Power Network Synthesis (PNS), Integer Linear Programming (ILP), Power Gating Designs |
| 相關次數: | 點閱:101 下載:0 |
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電源門控(power gating)是低功耗設計中的一項重要技術,其中電路被劃分為多個電源域(power domains),以便可以獨立關閉每個電源域的電源供應。然而,這使得電源網絡規劃變得更為複雜,因為不同電源域中的電源網不能重疊。為了加速這一過程,本篇論文提出了一種方法,能夠自動為每個電源域合成各自的電源供應網絡,同時最小化晶片整體的電壓降。首先,我們的方法會為每個電源域建立一個生成圖(spanning graph),其中包含所有可能的電源供應路徑。然後,我們使用整數線性規劃來決定合適的電源供應路徑數量以及其繞線拓撲(routing topology)。最後,我們會通過更改連接點來優化繞線路徑,避免這些路徑被其他網絡阻擋導致最終繞線失敗。實驗結果顯示與貪婪方法(greedy approach)相比,我們的方法在工業設計中能夠得到更少的電壓降。
Power gating is an important technique in low-power designs, where circuits are partitioned into several power domains (PDs) so that the power supply in each PD can be turned off independently. However, this complicates powerplanning since power nets in different PDs cannot cross. To expedite this process, this thesis proposes an automatic approach to synthesizing a power delivery network (PDN) for each PD to minimize IR-drop. First, a spanning graph is constructed for possible power delivery paths in each PD. Then, we apply integer linear programming (ILP) to determine the suitable number of power delivery paths (PDPs) and their routing topologies. Finally, we refine the routing paths by changing the connection points if they are blocked by other nets. Experimental results show that our method results in less IR-drop compared to a greedy approach in industry designs.
[1] W.-H. Chang, M. C.-T. Chao, and S.-H. Chen, “Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer,” in IEEE TVLSI, vol. 22, no. 5, pp. 1069-1081, May. 2014.
[2] H. Chen, C.-K. Cheng, A. B. Kahng, Q. Wang and M. Mori, “Optimal Planning for Mesh-Based Power Distribution,” in Proc. of ASP-DAC, pp. 444-449, Jan. 2004.
[3] J.-X. Chen, S.-T. Liu, Y.-T. Wu, M.-T. Wu, C.-M. Li, N. Chang, Y.-S. Li and W.-T. Chuang, “Vector-based Dynamic IR-drop Prediction Using Machine Learning,” in Proc. of ASP-DAC, pp. 202-207, Jan. 2022.
[4] W.-H. Chang et al., “Generating Routing-Driven Power Distribution Networks with Machine-Learning Technique,” in IEEE TCAD, vol. 36, no. 8, pp. 1237-1250, Aug. 2017.
[5] C.-C. Huang, C.-T. Lin, W.-S. Liao, C.-J. Lee, H.-M. Chen, C.-H. Lee and D.-M. Kwai, “Improving power delivery network design by practical methodologies,” in Proc. of ICCD, pp. 237-242, Oct. 2014.
[6] D. Hyun, W. Lee, J. Park, and Y. Shin, “Integrated Power Distribution Network Synthesis for Mixed Macro Blocks and Standard Cells,” in IEEE TCAS-II, vol. 70, no. 6, pp. 2211–2215, Jun. 2023.
[7] Y. Jung, D. Hyun, S. Choi and Y. Shin, “Power Distribution Network Optimization Using HLA-GCN for Routability Enhancement,” in Proc. of ICCAD, pp. 1-8, Oct. 2023.
[8] S. Kose and E. G. Friedman, “Fast Algorithms for IR Voltage Drop Analysis Exploiting Locality,” in Proc. of DAC, pp. 996-1001, Jun. 2011.
[9] J.-M. Lin, Y.-T. Chen, Y.-T. Kung and H.-J. Lin, “Voltage-Drop Optimization Through Insertion of Extra Stripes to a Power Delivery Network,” in Proc. of ISPD, pp. 35-43, Mar. 2023.
[10] J.-M. Lin, Y.-T. Kung, Z.-Y. Huang and I-R. Chen, “A Fast Power Network Optimization Algorithm for Improving Dynamic IR-Drop,” in Proc. of ISPD, pp. 91-98, Mar. 2021.
[11] J.-M. Lin, J.-S. Syu and I.-R. Chen, “Macro-Aware Row-Style Power Delivery Network Design for Better Routability,” in Proc. of ICCAD, pp. 1-8, Nov. 2018.
[12] S. S.-Y. Liu, C.-J. Lee, C.-C. Huang, H.-M. Chen, C.-T. Lin and C.-H. Lee, “Effective Power Network Prototyping Via Statistical-Based Clustering and Sequential Linear Programming,” in Proc. of DATE, pp. 1701-1706, Mar. 2013.
[13] H. Qian, S. R. Nassif and S. S. Sapatnekar, “Random Walks in a Supply Network,” in Proc. of DAC, pp. 93-98, Jun. 2003.
[14] H. Su, J. Hu, S. Sapatnekar, and S. Nassif, “Congestion-Driven Codesign of Power and Signal Networks,” in Proc. of DAC, pp. 64–69, Jun. 2002.
[15] H. Su, K. H. Gala and S. S. Sapatnekar, “Fast Analysis and Optimization of Power/Ground Networks,” in Proc. of ICCAD, pp. 477-480, Nov. 2000.
[16] S. X. D. Tan, C. J. R. Shi and J.-C. Lee, “Reliability-Constrained Area Optimization of VLSI Power/Ground Networks Via Sequence of Linear Programmings,” in IEEE TCAD, vol. 22, no. 12, pp. 1678-1684, Dec. 2003.
[17] T.-Y. Wang and C. C.-P. Chen, “Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm,” in Proc. of ISQED, pp. 157-162, Mar. 2002.
[18] Y. Zhong and M. D. F. Wong, “Fast Algorithms for IR Drop Analysis in Large Power Grid,” in Proc. of ICCAD, pp. 351-357, Nov. 2005.
[19] IBM ILOG CPLEX Optimizer, https://www.ibm.com/products/ilog-cplex-optimization-studio/cplex-optimizer.
[20] Realtek Inc., https://www.realtek.com.
校內:2029-09-20公開