本論文研究主題為結合小波轉換與訊號子空間分析在語音信號強化之應用，內容涵蓋軟體演算法的提出與硬體架構的設計。
在軟體的演算法方面，我們展示三個基於訊號子空間分析的語音強化技術。這三個方法分別為：1. 使用小波封包轉換於訊號子空間語音強化、2. 基於聽覺分頻與訊號子空間追蹤法的語音強化 、和3. 利用噪訊比及多頻帶的人耳聽覺遮蔽效應分析的語音強化。訊號子空間的分解是極為耗時的運算，因此，在第一個方法中，我們利用小波封包來做近似的Karhunen-Loeve轉換，亦即快速的本徵值分解來減低運算量，並將其應用在訊號子空間的語音強化。在第二個方法中，我們結合小波聽覺分頻分析與訊號子空間分解來實現語音強化。此一聽覺分頻係利用小波封包轉換來逼近人耳的聽覺頻帶，而此方法中的訊號子空間分解則是利用訊號子空間追蹤法來完成。經由TAICAR資料庫實驗驗證，我們研究中所提出的方法比起傳統訊號子空間強化法，更適用於車內噪音消除，低頻噪音能更有效抑制。在第三個方法中，我們基於第二個演算法的多頻設計，著重在每個次頻帶的增益調整。次頻帶的增益調整，決定噪音消除的效能，我們設計的增益調整考量到了噪訊比及人耳聽覺遮蔽效應。在實驗中，此一方法的效能表現，比起傳統訊號子空間強化法、頻譜相減法更為優越。
在硬體架構的設計方面，我們展示了一個二維小波轉換的硬體架構設計和訊號子空間語音強化法的單晶片系統架構設計。二維小波轉換的硬體架構設計可分為：基於列向和基於區塊兩類。基於列向的硬體設計有著低複雜度的優點，但在二維訊號的應用中，有著下述缺點：大量資料緩衝的記憶體需求和資料輸出有著較長的潛伏期。在本論文中，我們提出了一個基於區塊的二維小波轉換硬體設計，支援JPEG2000標準且跟基於列向的硬體設計比較起來，有著低緩衝、短潛伏期的優勢及近乎100%的硬體使用率。此一系統已實現於ALTERA EPXA10發展版上，時脈運作為44.33MHz。另外，在語音訊號即時處理的應用上，我們提出了一個單晶片系統架構，其內含管線化訊號子空間追蹤法的VLSI硬體設計。此一系統也實現於ALTERA EPXA10發展版上，時脈運作為9.7MHz，在效能分析上能符合即時系統的運作。

This dissertation presents a research on wavelet transform and signal subspace speech enhancement from algorithms to hardware implementations.
In the design of algorithms, we present three subspace-based approaches for speech enhancement. These approaches are signal subspace speech enhancement using wavelet packet expansion (SSUW), speech enhancement using critical band and subspace tracking (CBST), and SNR and auditory masking aware technique for multiband speech enhancement (SAMA). The decomposition of signal subspace is a time-consuming processing. In the algorithm of SSUW, we utilize wavelet packet to perform approximate Karhunen-Loeve transform, i.e., fast eigendecomposition for signal subspace speech enhancement to overcome this problem. In the algorithm of CBST, we incorporate a perceptual wavelet filterbank that is derived from psycho-acoustic model with signal subspace processing. The projection approximation subspace tracking deflation (PASTd) algorithm is used to track the signal subspace. The experimental results which were obtained by testing TAICAR databases show that this approach is better than conventional subspace methods. The low frequency noises in car noisy environments are suppressed efficiently after applying the perceptual filterbank and subspace processing. In the algorithm of SAMA, we focus our design on the gain adaptation of each critical band. The gain adaptation plays a crucial role in the critical band signal estimation. An attenuation factor based on auditory masking and prior SNR of each critical band is presented to adjust the estimator’s gain. According to the experimental evaluation, our method achieved enhancement performances better than conventional subspace and spectral subtraction methods.
In the design of VLSI architecture, a hardware design of 2D discrete wavelet transform (DWT) and system-on-a-programmable-chip (SoPC) architecture of subspace based speech enhancement are presented respectively. 2D DWT architectures can be classified into line-based and block-based architectures. Line-based architectures are simple with low complexity. They are efficient for 1D applications. In case of 2D transforms, they suffer from two main problems: memory requirements and latency. These problems are inherent in line-based architectures. In this dissertation, a novel block-based architecture for computing the lifting-based 2-D DWT coefficients is presented. This architecture makes the significant reduction of buffer size and speeds up the calculation of 2D wavelet coefficients as compared with those line-based fashion architectures. In addition, the proposed architecture supports the JPEG2000 default filters and the hardware utilization is nearly 100%. As compared with line-based architectures, the latency is reduced from N^2 down to 3N. The architecture has been realized in ARM-based ALTERA EPXA10 Development Board with frequency at 44.33MHz. For real-time speech enhancement, a SoPC architecture and VLSI design of the PASTd algorithm are proposed. To realize pipeline computation, we present a pipelined PASTd algorithm without data-dependent hazards. The maximum clock rate is 9.7 MHz and the typical clock rate which achieves real time requirement is 4.6 MHz. The corresponding architecture was also experimentally verified via an ALTERA EPXA10 development board.

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