以系統單晶片(SoC)來實現複雜的系統已成為積體電路設計的主要趨勢。為了實現完整的系統於單一晶片中，愈來愈多的類比與混合訊號電路被整合於晶片內。隨著產品設計複雜度的提升以及全球電子產品平均生命週期縮短，積體電路設計者所面臨的挑戰也愈來愈加劇，如何開發有效率之電路設計自動化軟體，以加速類比與混合訊號電路的設計時程，其重要性愈趨顯著。類比數位轉換器為系統單晶片中最常見的混合訊號電路之一，在所有高速類比數位轉換器中，管線式類比數位轉換器因具有高速操作、高解析度與低功率消耗的特性，廣泛的應用在行動通訊、視訊與影像處理系統中，然而、其同時也具有較高的設計複雜度。因此，在本論文中，我們發展了一個管線式類比數位轉換器的自動化合成軟體，藉由統整以往電路設計的經驗，可使得自動化合成軟體在短期內設計出效能可接受的管線式類比數位轉換器。在使用兩個1.2GHz UltraSPARC-III+處理器與2GB記憶體的作業平台中，我們的軟體可在一天之內完成類比數位轉換器的全電路設計。

Using a system-on-chip to realize a complex system has become the main trend for today’s IC design. To realize a complete system on a single chip, there are more and more analog and mixed-signal circuits integrated in the chip. With the increasing complexities of SoC designs and the shortening average life-periods of electronic products, it is getting harder to complete a SoC design within a very tight design schedule. Therefore, developing design automation tools for mixed-signal circuits to speedup the design process is more and more important. Analog-to-digital converter is one of the most commonly used components in a mixed-signal SoC. Among all architectures of high-speed analog-to-digital converters, the pipelined analog-to-digital converter is widely used in the applications of mobile communication, display, and imaging systems because it exhibits properties of high-speed, high-accuracy and low power consumption. However, its design complexity is higher then other architectures of analog-to-digital converters. In this thesis, we develop an automated synthesis tool for pipelined ADCs by consulting the circuit-design experience. It can be used to design a pipelined ADC with acceptable performances in a short time. Experimental results show that it can complete the design of the whole pipelined ADC circuit in one day on the operating system with two 1.2GHz UltraSPARC-III+ processor and 2GB memory.

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