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研究生： 曾慧欽
Tseng, Hui-chin
論文名稱： 一個以補數平均值方法實現之低功率軌對軌六位元快閃式類比數位轉換器
A Low Power Rail-to-Rail 6-bit Flash ADC Based on a Novel Complementary Average-Value approach
指導教授： 劉濱達
Liu, Bin-Da
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2004
畢業學年度： 92
語文別： 英文
論文頁數： 71
中文關鍵詞： 快閃式類比數位轉換器 、軌對軌 、低功率
外文關鍵詞： low power, flash ADC, rail-to-rail
相關次數： 點閱：105  下載：2 
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    • 　　在本論文中，我們提出一新穎之補數平均值(CAV)方法用來實現一個六位元、300 MSample/s (MS/s)之快閃式類比/數位轉換器。將輸入信號經預先處理後，產生一個階梯式之輸入訊號與一固定之電壓作比較，以大幅簡化比較器之設計，進而降低功率消耗。此外，透過此CAV之方法可達到軌對軌之輸入電壓範圍，並且由於比較器之設計相當一致，因此可大幅降低製程上所造成之偏移電壓，進而消除氣泡所造成之錯誤。
    　　本論文所設計之類比數位轉換器是實現於TSMC 1P5M 0.25微米製程，模擬結果可達INL<0.4 LSB、DNL<0.1 LSB、並達33.08 dB SNDR。此類比數位轉換器於供應電壓2.5 V下消耗42 mW，且其功率效率為3.96 pJ/conv-step，此效果優於其它快閃式類比數位轉換器之著作。

    　　In this thesis, a 6-bit 300 MS/s flash ADC based on a novel Complementary Average-Value (CAV-Based) approach is proposed. Input signal is pre-processed and then compare with a fixed reference voltage level, which greatly simplifies the comparator design and thus saves power. In addition, rail-to-rail input range can be achieved by the technique, the offset and thus bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25-μm process parameters, the results show that INL < 0.4 LSB and DNL < 0.1LSB, and achieve 33.08 dB SNDR. The converter consumes 42 mW at 2.5 V power supply and the power efficiency of this converter is only 3.96 pJ/conv-step which compares favorably with other published results.

    1 Introduction 1 1.1 Motivation 1 1.2 Organization of the Thesis 2 2 Review of High-Speed Analog-to-Digital Converters 4 2.1 Introduction 4 2.2 A/D Conversion 4 2.2.1 Direct Quantization 5 2.2.2 Quantization after Analog Preprocessing 6 2.3 ADC Performance Metrics 7 2.3.1 Resolution 8 2.3.2 Signal to Noise Ratio 8 2.3.3 Signal to Noise + Distortion Ratio 11 2.3.4 Dynamic Range 11 2.3.5 Nonlinearity 12 2.4 Review of ADC Architecture 15 2.4.1 Flash (Parallel) ADC 15 2.4.2 Subranging ADC 16 2.4.3 Folding-and-Interpolating ADC 18 2.4.4 Pipeline ADC 23 2.5 Summary 24 3 Circuit Design of Rail-to-Rail CAV-Based Flash A/D Converter 26 3.1 Introduction 26 3.2 Conventional Flash ADC 27 3.3 Proposed CAV-based Approach 29 3.4 Reference ladder with CAV unit Design 32 3.5 Comparator Design Basics 33 3.5.1 Static Characteristics 33 3.5.2 Dynamic Characteristic 37 3.6 Two-Stage Comparator with Inverter Chain 41 3.7 Latched Comparator Design 42 3.7.1 Preamplifier with Reset Switch 43 3.7.2 First Stage Comparator 48 3.7.3 Second Stage Comparator 49 3.8 Digital Encoder design 50 3.8.1 Digital Encoder Block and Timing Diagram 51 3.8.2 One-of-n encoder 53 3.8.3 Quasi-Gray Encoder Design 54 3.9 Layout and Floor Plan 56 3.10 Summary 58 4 Simulation Results 59 4.1 Static Performance Evaluation 59 4.2 Dynamic Performance Evaluation 61 5 Conclusions and Future Work 65 5.1 Conclusions 65 5.2 Future Work 66 6 References 67

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