在元件閘極氧化層厚度快速縮小的趨勢下，氧化層厚度薄至20Å以下時元件會因為直接穿遂效應而產生很大的閘極漏電流。因此，尋找高介電係數（High-k）閘極介電層材料以替代原先二氧化矽介電層，是當今非常重要的一個課題。然而在材料替換的過程中，諸多不可預期的問題開始產生如電荷捕獲（charge trapping）造成啟始電壓（threshold voltage）飄移與載子遷移率（mobility）的下降等，因此值得探討高介電係數閘極介電層元件其界面陷阱密度對於電性的影響。本論文我們選擇利用電荷汲引技術為架構發展出可以觀察High-k元件進行不同製程條件之後所產生的界面陷阱密度。我們發現使用二氧化矽結合氮氧矽酸鉿介電層元件比使用氮氧化矽與氮氧矽化鉿介電層元件具有較低的界面陷阱電荷、較薄的等效氧化層厚度。而因為氮氧化矽界面之介電層元件有較薄的物理厚度所以其閘極漏電流較高，而其具有較低的界面陷阱密度所以有較高的電子遷移速度。在我們的實驗中也探討氨氣和氮氣用於高介電係數閘極介電層材料電漿氮化的影響，發現氮氣是較好的選擇，因為氮氧矽酸鉿介電層材料中矽原子容易與氨氣中的氫作鍵結，但是鍵結不穩定而容易形成斷鍵的存在，而這樣的化學反應會對於電荷的捕捉及散射影響較為嚴重。最後探討元件電特性和熱退火的影響。我們發現經過在氮環境下850oC 60秒退火後的元件具有較低的界面陷阱密度並可減少氮氧矽化鉿之矽懸鍵與降低N≡N數量，結果指出使用氮氣電漿氮化再搭配熱退火的處理，可有效降低電荷被捕捉的機率降低漏電流以及提升載子移動率。

The aggressive CMOS device scaling has been reaching the physical limit of conventional SiO2 MOSFETs. When the dielectric thickness less than 20Å, the directly tunneling will induce higher leakage current. It is important to find a gate dielectric which could attain most of the merits of SiO2 and high temperature reliability. Essentially, such a candidate should be considered the impact of device characteristics (threshold voltage shift and mobility degradation ) by the charge trap.In this work, we have presented our recent results of HfSiON gate dielectric subjected to various nitridation and PNA treatments. The extracted effective trap density (Nit) of devices are based on charge pumping (CP) measurements. Effect of interface layer (IL) on the electrical characteristics of the HfSiON/IL high-k gate stacks and mobility degradation in nMOSFETs were analyzed and discussed. The IL thickness was found to have a profound effect on the leakage current reduction. The DI-O3 IL has thinner physical thickness than N2O Plasma IL .Since leakage current of the thin dielectric is governed by tunneling mechanism, even the DI-O3 chemical oxide can have better quality oxide interlayer on the Si interface as compared with N2O plasma oxidation interlayer. NH3 plasma can have better dissociation than N2 plasma. But the presence of residual hydrogen coming from NH3 gas has deleterious affects on the charge trapping behaviors of MOSFET devices. After N2 ambient at 850oC for 60s annealing, the N≡N bonds were almost completely eliminated from High-k nitrided film and leaving only strong Si-N bonds. Nitrogen incorporated Hf-silicate dielectric using N2 plasma nitridation with PNA is promising to improve film quality by reducing charge trapping characteristics, improved drain current and enhancing mobility.

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