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研究生：	黃琮淵 Huang, Tsung-Yuan
論文名稱：	應用於多種視訊用途之可重組反轉換架構之設計與實現 Design and Implementation of Reconfigurable Inverse Transform Architecture for Multiple Purpose Video Coding
指導教授：	李國君 Lee, Gwo-Giun
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2010
畢業學年度：	98
語文別：	英文
論文頁數：	67
中文關鍵詞：	多規格、可重組、複雜度分析、資料流
外文關鍵詞：	multiple standards, reconfigurable, complexity analysis, dataflow
相關次數：	點閱：116 下載：0
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在這篇論文中，我們提出一個可應用於多規格用途的可重組逆轉換架構以及一個用於 AVC/H.264 的可重組 Hadamard 轉換。藉由伴隨複雜度分析以及資料流建模之由上而下的設計方式以及萃取演算法之間的共通性。透過探索之共通性，提出之可重組設計可以節省 44%的加法器使用量並且有能力去支援包含於MPEG-2 標準中之逆離散餘弦轉換以及 AVC/H.264 標準中所用到的整數逆轉換。此架構透過 TSMC 0.18 微米製程技術合成，工作頻率為 108MHz，其中工作頻率的選擇為透過資料流排程得到的結果。提出之設計的合成面積為 32K 閘,可以看出設計之架構於 VLSI 實現中相較於相關之設計中能有比較好的面積效益。除此之外，提出之逆轉換架構的精度需求能夠符合IEEE1180-1990和ISO/IEC 23002-1標準中的精度規範。因此，基於我們的由上而下的設計方式以及萃取共同性，提出之設計能有較低的面積成本以及足夠的彈性來使用於目標規格為 1920×1088之影像解析度，每秒64張楨圖，以及色彩格式為4:2:0的多規格用途上。

In this thesis, an area efficient reconfigurable inverse transformation architecture for multiple standards and a directed 2D reconfigurable Hadamard transform architecture for AVC/H.264 are proposed. We present top down design methodology with complexity analysis, commonalities extraction, and dataflow modeling to design reconfigurable architecture. By sharing the commonalities,the adder usage of the proposed reconfigurable inverse transform datapath can be reduced 44% compared with total amount of adders in performing transforms. Then, the reconfigurable architecture is synthesized using TSMC 0.18 technology cell library. The working frequency is 108Mhz, which is derived from the dataflow. The area synthesis result is 32k gates, which indicates that the proposed design has more efficient area than other documented design in VLSI implementation. In addition, the proposed architecture also satisfies the accuracy requirement of IEEE1180-1990 and ISO/IEC 23002-1 specification. Therefore, based on our top-down design approach and commonality extraction, the proposed designs have lower hardware cost and enough flexibility for multi-standard purposes with 1920×1088 resolution and 64 frames per second and the color format is 4:2:0 for real time processing.

Abstract ii 
Table of Contents iv 
List of Tables vii 
List of Figures viii 
Chapter 1  Introduction 1 
1  Background 1 
2  Motivation 2 
3  Organization of this Thesis 2 
Chapter 2  Overview of Transforms Used in MPEG-2 and AVC/H.264 3 
1  Introduction to Transform Adopted in MPEG-2 3 
1.1  DCT/IDCT Properties 4 
1.2  IDCT Implementation Issues 5 
1.3  Measure Accuracy Procedure 6 
2  Introduction to transform in AVC/H.264 7 
2.1  AVC/H.264 Decoding Flow  7 
2.2  Introduction to Transforms Adopted in AVC/H.264 8 
2.2.1  Integer 4×4 transform 8 
2.2.2  4×4 Hadamard transform 10 
2.2.3  2×2 Hadamard transform 11 
2.2.4  Integer 8×8 transform 12 
Chapter 3  Introduction to fast transform algorithms and architectures 13 
1  Fast transform algorithms 13 
1.1  Chen’s Factorization 14   
1.2  Lee’s Factorization 14 
1.3  Fast Inverse Integer Transforms in AVC/H.264 16 
1.3.1  Inverse 4×4 transform 16 
1.3.2  Inverse 8×8 transform 17 
1.3.3  Inverse Hadamard Transform 18 
2  Transform architectures 20 
2.1  Distributed Arithmetic 20 
2.2  CSHM Architectures 20 
2.3  CORDIC Architectures 21 
Chapter 4  Reconfigurable Inverse Transformation Architecture Design 23 
1  Reconfigurable Video Coding (RVC) 23 
2  Specification 24 
3  Proposed Fast IDCT for MPEG-2 25 
3.1  Scaling Factor Derivation 29 
3.2  Accuracy measurement 29 
4  Directed 2D Hadamard Transform 31 
5  Commonality extraction 33 
6  Complexity Analysis 34 
6.1  Number of Operation 34 
6.2  Degree of Parallelism 36 
6.3  Pipeline depth 38 
7  Design Space Exploration 39 
7.1  High Level Design Space Exploration 40 
7.1.1  16×16 Granularity 40 
7.1.2  16×8 Granularity 40 
7.1.3  8×8 Granularity 41  
7.1.4  8×4 Granularity 43 
7.1.5  Conclusion of High Level Design Space Exploration 44 
7.2  Low Level Design Space Exploration 44 
7.3  Design Space Exploration with Complexity Analysis 49 
8  Architecture Design and Implementation 50 
8.1  Block Diagram of Reconfigurable IQIT module 51 
8.2  Transpose Memory 52 
8.3  Reconfigurable Inverse Transform Data Path 53 
8.4  Reconfigurable Hadamard Transform(RHT) Data Path 56 
Chapter 5  Verification and Experimental Results 58 
1  Verification Process 58 
1.1  Dataflow model verification 59 
1.2  Register Transfer Level Verification 59 
1.3  Gate Level Netlist Verification 60 
2  Experimental Result 60 
3  Comparison with related works 62 
Chapter 6  Conclusion and future work 63 
1  Conclusion 63 
2  Future Work 64 
Reference  65 
                                    

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