本論文以TSMC 0.18um 1P6M CMOS製程來研製應用於802.11a WLAN之5GHz U-NII頻帶降頻器CMOS RFIC。降頻器規劃上，射頻為U-NII頻帶高頻段5.725~5.825GHz，經本地振盪(5.465~5.525GHz)降至中頻280MHz。參考WLAN規範，因應系統高線性度、低相位雜訊、高工作頻率等特性，設計射頻前端接收電路。晶片採用打鎊線到FR-4基板上進行量測。低雜訊放大器量測所得增益約6.4dB，雜訊指數為4.9dB，input P1dB為-5.25dBm；單端平衡混波器量測所得轉換損耗為4.5dB，雜訊指數為14.6dB，input P1dB為0dBm；L-C tank壓控振盪器量測所得輸出頻率為5860~6026MHz，相位雜訊-85dBc/Hz@100KHz；四相位輸出壓控制振盪器量測所得輸出頻率為6341~6382MHz，相位雜訊-87dBc/Hz@100KHz；雙模數(32/33)除頻器，量測所得在mode=0時，最高操作頻率為7225MHz，mode=1時，最高操作頻率為6800MHz。CMOS RFIC量測結果與ADS、H-Spice模擬接近符合。
在TSMC 0.18um 1P6M CMOS製程的RF model已趨於準確以及穩定下，透過小心的設計及佈局，均可得到不錯的5GHz電路特性。若能再加入精準的偏壓電路，仔細考慮雜訊阻絕以及電路間的隔離，應可成功將5GHz CMOS晶片做更進一步的整合。

This thesis presents the development of 5GHz U-NII band CMOS RFICs for the 802.11a WLAN receiver down-converter in TSMC standard 0.18um CMOS technology. The developed 5GHz RFICs include the LNA, mixer, L-C tank and quadrature VCOs, and prescaler for 5GHz synthesizer. The RF is from 5.725 to 5.825 GHz, the LO is 5.465 to 5.525GHz and the IF is at 280 MHz. The measurements are performed by using FR-4 PCB test fixture. The LNA has 6.4dB gain, 4.9dB noise figure and input P1dB -5.25dBm. The single-balanced mixer has 4.5dB conversion loss, 14.6dB noise figure and input P1dB 0dBm. The L-C tank VCO has output frequency from 5860 to 6026MHz with
-85dBc/Hz@100KHz phase noise. The quadrature VCO has output frequency from 6341 to 6382MHz with
-87dBc/Hz@100KHz phase noise. The dual-modulus prescaler (32/33) has highest operating frequency at 7225MHz and 6800MHz, respectively, when mode is 0 and 1. The circuit design simulation is performed by using ADS and H-Spice. Simulation and measured results basically agree well.

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