本論文提出了一種應用於語音活動檢測之切換式電容聲音特徵萃取器設計。為了克服PVT變化衍生的問題，在系統中選擇開關式電容濾波器來實現電路，也透過運算放大器共享技術來降低功率消耗。除此之外，將頻帶從16個減少到6個，系統可以在不需要犧牲語音活動偵測正確率的情況下進一步降低功率消耗。
本次研究總共實現了兩顆晶片，包含了前端的特徵萃取電路以及整合型的語音活動檢測器。第一顆特徵萃取晶片以台積電180奈米CMOS製程製造，晶片中核心電路面積為0.65 mm2，在1.8伏特供應電壓下，功率消耗為2 μW。使用基於類神經網路實現的軟體端分類器對聲音以及噪音做辨識。在3dB信噪比的輸入訊號下，語音成功判斷率為97%，噪音誤觸率為3.8%，延遲時間為30毫秒。
第二顆整合型語音活動檢測器晶片，實作包含了特徵萃取電路與使用類神經網絡實現的分類器。晶片以台積電180奈米CMOS製程製造，晶片中核心電路面積為1.104 mm2，在1.8伏特供應電壓下，功率消耗為2.66 μW。在3dB信噪比的輸入訊號下，語音成功判斷率為97%，噪音誤觸率為3.4%，延遲時間為32毫秒。

This thesis presents a low-power acoustic feature extractor (AFE) for voice activity detection (VAD). To overcome the effect of Process-Voltage-Temperature (PVT) variations, a switched-capacitor (SC) band-pass filter (BPF) with the op-amp sharing technique is presented in this work to save power consumption. In addition, further reduction on power consumption is achieved by reducing the frequency bands from 16 to 6 without scarifying the voice activity detection accuracy of the whole system.
Two proof-of-concept chips are realized in this work, including an analog feature extractor (AFE) circuit and an integrated voice activity detector (VAD). The AFE chip is fabricated in 180-nm CMOS process, has a core area of 0.65 mm2 and consumes 2 μW under a 1.8-V supply voltage. Using a software neural network based classifier to distinguish the voice from background noise, it achieves an average of 97% voice detected as voice (VDV) and 3.8% noise detected as voice (NDV) at a 3dB signal-to-noise ratio (SNR) with 30 ms latency.
The VAD chip merges the AFE with a hardware classifier. The classifier is implemented based on an in-memory-computation neural network. The VAD chip is also fabricated in a 180-nm CMOS process, has a core area of 1.104 mm2 and consumes 2.66 μW under a 1.8-V supply voltage. Experiment results show that the proof-of-concept prototype achieves an average of 97% VDV and 3.4% NDV at a 3dB SNR with 32 ms latency.

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