本論文提出具最佳化回授電路之遲滯電容電流控制直流-直流降壓轉換器以同時達到最佳化輸入電壓/負載電流/動態電壓調節暫態響應。因為其固有的最佳化輸入電壓暫態性能，具積體化電容電流感測器之遲滯控制為使用的控制模式。而根據時域的分析，具有非線性回授之最佳化回授電路被提出來最佳化負載電流/動態電壓調節暫態響應。此外，誤差放大器提供了良好的調節律效能，而暫態保留技術減少誤差放大器對於電容值的需求以減小控制器面積。能量回收機制將多餘的輸出電容能量回收至輸入端，負載電流/動態電壓調節暫態響應也因此不受到小負載電流的限制。
本晶片由0.35-μm CMOS 所完成，面積為0.88mm2。1-V 輸入電壓暫態響應量測出可忽略的輸出擾動。對於500-mA負載電流，輸出電壓在0.8 μs內穩定。對於0.6-V動態電壓調節，輸出電壓在3μs內穩定。輸入電壓調節率為2.5mV/V而負載調節率為0.5mV/A。最大負載電流可達2A而在輸出功率為500mW時量測到最大效率96%。

A hysteretic capacitor current control DC-DC buck converter with transient-optimized feedback circuit is presented to simultaneously achieve optimal line/load/DVS transient responses. The hysteretic control with an on-chip capacitor current sensor (CCS) is adopted for its inherent well line transient performance. According to time-domain analysis, a transient-optimized feedback circuit (TOFC) with non-linear feedback is proposed to optimize load/DVS transient responses. Moreover, the error amplifier improves the regulation performance and a transient-hold (TH) technique reduces the required capacitance of the error amplifier to save the controller area. An energy-recycled control (ERC) recycles the excess energy in the output capacitor to the input supply and thus load/DVS transient responses are not limited by small load current.
The fabricated chip occupies 0.88 mm2 in a 0.35-μm CMOS process. Measurement result shows negligible output disturbance in response to 1-V line voltage step. For 500-mA step-up load current, output voltage is settled within 0.8 μs. For 0.6-V DVS, output voltage is settled within 3 μs. The line regulation performance is 2.5mV/V and the load regulation performance is 0.5mV/A. The maximum load current is 2A and peak efficiency of 96% is measured at 500 mW output power.

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