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研究生: 翁柏聖
Weng, Po-Sheng
論文名稱: 渦輪碼之研究與硬體實現
Study and Implementation of Turbo Codes
指導教授: 蘇賜麟
Su, Szu-Lin
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2003
畢業學年度: 91
語文別: 英文
論文頁數: 63
中文關鍵詞: 最大事後機率實現渦輪碼
外文關鍵詞: MAP, implementation, turbo codes
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  • 本論文將研究渦輪碼的實現,並以德州儀器公司所出產的TMSC6711DSK完成硬體製作。實現渦輪解碼器(turbo decoder)時,必須考慮各種硬體實現會面臨到的問題。開始將討論對數化最大事後機率(Log-MAP)、最大對數化最大事後機率(Max-Log-MAP)及軟輸入/軟輸出維特比演算法(SOVA)三種最廣泛用來做為渦輪解碼器的演算法,各種演算法的差異與優劣將被比較與分析,以做為選擇適當的疊代解碼器演算法之依據。接著討論一個改良過的SOVA解碼方式,發現在某些情形下此方法的確比傳統的SOVA演算法得到更佳的位元錯誤率(BER)。
    為了設計一個定點數(fixed-point)計算之渦輪解碼器,量化(quantization)的效應也是應該考量的重要因素之一。然而,我們將透過理論探究與模擬去找出適當的量化處理方法。由於之前都是假設在已知通道訊息與完美同步的情形下,進行各種分析與討論。因此,最後也考慮訊號雜訊比量測(SNR estimate)與時間偏移(timing offset)的問題,希望可以找出適合於硬體實現的方法。

    This thesis intends to study and implement turbo codes with the TMS320C6711 processor. When implementing the decoder of turbo code, we shall consider various problems related to our hardware implementation. We start with a discussion on the most popular turbo decoding algorithms: Log-MAP, Max-Log-MAP and SOVA algorithms. We then select those decoding algorithms that may be suitable for an iterative decoder. A modified SOVA decoding scheme is proposed to give improved performance in BER. It will be compared with the conventional SOVA algorithm.
    We discuss the effect of quantization and give a suitable design for our fixed-point design of turbo decoders. The previous method for decoding turbo codes is analyzed under the assumption of perfect channel information and synchronization. Thus, we give consideration to the problems of SNR estimate and timing offset in the end.

    Abstract I Contents II List of Tables IV List of Figures V Chapter 1 Introduction 1 Chapter 2 An Introduction of Turbo Codes and Turbo Codes in 3GPP2 Standard 2 2.1 Introduction of Turbo Codes 2 2.2 Turbo Codes in 3GPP2 Standard 4 2.2.1 Turbo Encoding………………………………………………………….4 2.2.2 Rate 1/2, 1/3 and 1/4 Turbo Encoders...………………………………...5 2.2.3 Turbo Code Termination...………………………………………………5 2.2.4 Turbo Interleavers ...……………………………………………………..6 Chapter 3 Decoding Algorithm 10 3.1 Iterative Decoder Structure……………………………………………………..10 3.2 The Maximum A-Posteriori Algorithm………………………………………...10 3.3 The Max-Log-MAP Algorithm………………………………………………….17 3.4 The Log-MAP Algorithm………………………………………………………..19 3.5 The SOVA Algorithm……………………………………………………………19 3.6 Simulation Results………………………………………………………………21 Chapter 4 SOVA Algorithm 25 4.1 Overview…………………………………………………………………………...25 4.2 The difference between Forward and Backward SOVAs………………………25 4.3 Serially Mixed SOVA……………………………………………………………..28 4.4 Complexity………………………………………………………………………...30 Chapter 5 Fixed-Point Iterative Decoder 31 5.1 System Model………………………………………………………………………31 5.2 Integer representation of LLRs…………………………………………………...32 5.3 Integer Representation of Extrinsic Values………………………………………35 5.4 Internal Precision of the SISO Algorithm………………………………………..36 Chapter 6 SNR Mismatch and SNR Estimation in Turbo Decoding 39 6.1 Overview……………………………………………………………………………39 6.2 SNR Sensitivity…………………………………………………………………….39 6.3 SNR Estimation……………………………………………………………………42 Chapter 7 Synchronization 44 7.1 System Model…………..………………………………………………………….44 7.2 The Synchronization Algorithm………………………………………………….45 7.3 ML NDA Range Detection………………………………………………………..47 7.4 Soft Bit Distribution………………………………………………………………49 7.5 Soft bits Combining………………………………………………………………50 Chapter 8 Hardware Implementation 52 Chapter 9 Conclusion 59 Bibliography 60

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