在本論文中，我們提出了一個可同時針對多種錯誤模型同時產生測試向量的方法。所考慮的錯誤模型包含定值錯誤、靜態橋接錯誤、延遲錯誤及電晶體無法導通錯誤。所有目標錯誤皆會被轉換為具有特定限制的定值錯誤，並配合我們提出之具有兩個時間框架的電路模型，使得所需測試資料可以一次性的被自動向量生成軟體產生。此方法突破了目前商用測試向量生成軟體中無法同時產生單向量及雙向量測試所需之測試資料的限制。此外所生成的測試向量能被多種錯誤模型共用，故測試資料量及測試資料輸入時間能被大幅降低。本方法可支援生成LOC或LOS測試向量格式，此兩者為最常被使用於雙向量測試之格式。最後本論文中所使用之具有兩個時間框架的電路模型僅用於測試資料生成，故無須在實際設計中額外增加任何電路。在ISCAS’89、IWLS’05及ITC’99的實驗結果顯示在使用LOC測試向量格式下與最高效率的傳統方法相比，我們的方法可以分別降低14.02%、12.12%及12.97%的測試資料量，同時也分別縮短21.54%、15.03%及16.3%的測試資料輸入時間。在生成LOS測試向量格式及N次偵測之測試向量的實驗結果中也顯示同時考慮多種錯誤模型生成測試資料的方法與傳統方法相比能節省更多測試成本。

In this thesis, a novel test pattern generation method for multiple DC and AC faults is presented. The fault models considered include stuck-at faults, bridging faults, transition faults and transistor stuck-open faults. All faults are transformed into stuck-at faults with some constraints in a proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model which is supported by most commercial ATPG tools. This makes it possible to generate all required patterns for both DC and AC faults in one ATPG run with no need to modify the ATPG tool. A highly compact pattern set can thus be obtained which requires smaller test data volume and shorter test application time. Traditional two-vector test schemes such as LOC and LOS are both supported. The proposed two-timeframe circuit model is needed only for ATPG tools to generate test patterns. Hence no logic is added to the real circuits. Experiments on ISCAS’89, IWLS’05 and ITC’99 benchmark circuits show that, compared to the most efficient conventional methods, on average our method can reduce test pattern counts by 14.02%, 12.12% and 12.97% and test application time by 21.54%, 15.03% and 16.3%, respectively, when the LOC test scheme is employed. Experimental results based on the LOS test scheme and the N-detect test method also show higher compaction by the proposed method over previous methods.

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