多輸入多輸出(Multiple input multiple output, MIMO)技術因為能提供較高的資料可靠度以及資料傳輸率，近來被大量採用在無線通訊系統上。為解決多輸入多輸出系統中訊號偵測的問題，許多不同的偵測方式例如：球形解碼(Sphere decoding)或K-Best演算法常被用來解析個別傳送天線所傳送的訊號。然而這些偵測演算法一般需要採用QR分解把原始的多輸入多輸出通道轉換為多層(Layer)的子通道，因此QR分解設計為多輸入多輸出通訊系統不可或缺的一部分。
本篇論文提出了一個採用改良式數位旋轉座標計算器(Coordinate rotation digital computer, CORDIC)的QR分解設計，此改良式計算器可以省略傳統計算器的第一次迭代，因此整體的輸出率可得到提升。此外，本論文亦在硬體設計中加入一個降低硬體複雜度的方法，因此可降低整體的硬體複雜度。實驗證實，我們所提出的適用於IEEE 802.11n系統之QR分解方法不但可增加輸出率且不會造成的誤碼率有明顯降低。根據硬體實現結果，若採用TSMC 0.18μm製程，所提出之QR分解設計可以操作在120MHz，且邏輯閘數目(Gate count)約為90.7K。

Multiple-input multiple-output (MIMO) techniques have been widely used in recent wireless communication systems since they can offer high data reliability and data transmission rate. To solve the problems of MIMO signal detection, MIMO detection schemes, such as sphere decoder or K-best algorithm, are often used to recover the signals from different transmit antennas. However, these detection schemes require QR decomposition (QRD) to convert a conventional MIMO channel into multiple layered subchannels. Therefore, QRD is necessary in the design of MIMO communication systems.
This thesis presents a QRD design with modified coordinate rotation digital computer (CORDIC) algorithm which avoids the operation of the first iteration in the original CORDIC algorithm. A hardware reduction method is also included in the proposed design to reduce the overall hardware complexity. Experimental results show that the proposed QRD design for IEEE 802.11n systems with modified CORDIC algorithm can increase the throughput rate without bit error rate (BER) degradation. Additionally, it can operate at 120 MHz using TSMC 0.18μm CMOS process and the total area requirement in terms of gate count is only 90.7K.

[1] A. J. Paulray, D. A. Gore, R. U. Nabar, and H. Bölcskei, “An overview of MIMO communications – A key to gigabit wireless,” Proc. IEEE, vol. 92, no. 2, pp. 198–218, Feb. 2004.
[2] S. Alamouti, “A simple transmit diversity technique for wireless communications,” IEEE J. Select. Areas Commun., vol. 16, pp. 1451–1458, Oct. 1998.
[3] V. Tarokh, N. Seshadri, and J. C. Belfiore,“On maximum likelihood detection and the search for the closet lattice point,” IEEE Trans. Inform. Theory, vol. 49, no. 10, pp. 2389–2402, Oct. 2003.
[4] E. Viterbo and J. Boutros,“A universal lattice code decoder for fading channels,”IEEE Trans. Inform. Theory, vol. 45, pp. 1639–1642, July 1999.
[5] M. O. Damen, A. Chkeif, and J. C. Belfiore,“Lattice code decoder for space – time codes,”IEEE Commun. Lett., vol. 4, pp. 161–163, May 2000.
[6] K. Wong, C. Tsui, R. Cheng, and W. Mow, “A VLSI architecture of a K-best lattice decoding algorithm for MIMO channels,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2002, pp. 273–276.
[7] M. Wenk, M. Zellweger, A. Burg, N. Felber, and W.Fichtner, “K-best MIMO detection VLSI architectures achieving up to 424Mbps,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2006, pp. 1151–1154.
[8] R. C.-H. Chang, C. H. Lin, K. H. Lin, C. L. Huang, and F. C. Chen, “Iterative decomposition architecture using the modified Gram–Schmidt algorithm for MIMO systems,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 5, pp. 1095–1102, May 2010.
[9] S. F. Hsiao and J. M. Delosme, “Householder CORDIC algorithms,” IEEE Trans. Comput., vol. 44, no. 8, pp. 990–1001, Aug. 1995.
[10] D. Patel, M. Shabany, and P. G. Gulak, “A low-complexity high-speed QR decomposition implementation for MIMO receivers,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2009, pp. 1409–1412.
[11] A. Maltsev, V. Pestretsov, R. Maslennikov, and A. Khoryaev, “Triangular systolic array with reduced latency for QR-decomposition of complex matrices,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2006, pp. 385–388.
[12] Z. Liu, K. Dickson, and J. V. McCanny, “Application-specific instruction set processor for SoC implementation of modern signal processing algorithms,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 4, pp. 755–765, Apr. 2005.
[13] Y. T. Hwang and W. D. Chen, “A low complexity complex QR factorization design for signal detection inMIMO OFDM systems,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2008, pp. 932–935.
[14] P. Luethi, A. Burg, S. Haene, D. Perels, N. Felber, and W. Fichtner, “VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2007, pp. 1421–1424.
[15] C. S. Wu and A. Y. Wu, “Modified vector rotational CORDIC (MVR-CORDIC) algorithm and architecture,” IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process., vol. 48, no. 6, pp. 548–561, June 2001.
[16] C. S. Wu, A. Y. Wu, and C. H. Lin “A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes,” IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process., vol. 50, no. 9, pp. 589–601, Sept. 2003.
[17] C. H. Lin and A. Y. Wu, “Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for scaling-free high-performance rotational operations,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 11, pp. 2385–2396, Nov. 2005.
[18] K. Maharatna, S. Banerjee, E. Grass, M. Krstic and A. Troya, “Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture.” IEEE Trans. Circuits Syst. Video Technol., vol. 15, no. 11. pp. 1463–1474, Nov. 2005.
[19] F. J. Jaime, M. A. Sánchez, J. Hormigo, J. Villalba, and E. L. Zapata, ”Enhanced scaling-free CORDIC,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 7, pp. 1549–1557, July 2010.
[20] C. Singh, S. Prasad, and P. Balsara, “VLSI architecture for matrix inversion using modified Gram-Schmidt based QR decomposition,” in Proc. Int. Conf. VLSI Design (ICVD), 2007, pp. 836–841.
[21] P. Salmela, A. Burian, H. Sorokin, and J. Takala, “Complex-valued QR decomposition implementation for MIMO receivers,” in Proc. Int. Conf. Acoustics, Speech, and Signal Process. (ICASSP), 2008, pp. 1433–1436.
[22] Z. Y. Huang and P. Y. Tsai, “Efficient implementation of QR decomposition for gigabit MIMO-OFDM systems,”IEEE Trans. Circuits Syst. I, Reg. Papers, to be published.
[23] P. K. Meher, J. Valls, T. B. Juang, K. Sridharan, and K. Maharatna, “50 years of CORDIC: algorithms, architectures and applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, No. 9, pp. 1893–1907, Sept. 2009.
[24] J. E. Volder, “The CORDIC trigonometric computing technique,” IRE Trans. Electron. Computers, vol. EC-8, pp. 330–334, Sept. 1959.
[25] J. E. Volder, “The birth of CORDIC,” J. VLSI Signal Process., vol. 25, pp. 101–105, 2000.
[26] J. S. Walther, “A unified algorithm for elementary functions,” in Proc. 38th Spring Joint Computer Conf. (SJCC), 1971, pp. 379–385.
[27] J. S. Walther, “The story of unified CORDIC,” J. VLSI Signal Process., vol. 25, no. 2, pp. 107–112, June 2000.
[28] Y. T. Hwang and W. D. Chen, “A fully parallel low complexity QR factorization design for MIMO OFDM system,” IET Circuits, Devices & Systems, to be published.