在許多訊號處理和通訊應用上，資料轉換器是個重要的輸出入介面。資料轉換器包括類比數位轉換器和數位類比轉換器。在本篇論文中，我們主要專注於數位類比轉換器的設計。對於高速應用，電流驅動式數位類比轉換器是最適合的架構之一。然而電流源的不匹配限制了數位類比轉換器的性能。大面積的電流源陣列可以維持電流源所需的精準度要求；但對於高頻信號，較大元件所附帶的寄生效應導致動態範圍的衰減。所以我們提出ㄧ個新的前景自我校正架構去克服此問題。這個校正技術不需要額外的高解析度類比數位轉換器，這將降低電路設計的複雜度。此外我們使用一個消除突波的技巧去降低在切換狀態時的突波效應。
在本篇論文中，一個具有低成本自我校正架構之十四位元每秒一億次取樣的電流驅動式數位類比轉換器已經被實現。他使用上述的前景自我校正技術去改善電流源的不匹配，並且縮小元件尺寸去降低對於高頻訊號之動態範圍的衰減。這樣做不但降低成本(晶片面積較小)也改善了電路的性能。這個數位類比轉換器採用台積電0.18微米、1P6M 混合訊號互補式金氧半導體製程，核心電路面積是0.99mm2。工作電壓是1.8伏，功率消耗是32毫瓦。

In many signal processing and telecommunication applications, Data converter is an important I/O interface. Data converter includes analog-to-digital converter (ADC) and digital-to-analog converter (DAC). In this thesis, we mainly focus in DAC design. For high speed application, the current-steering DAC is one of most suitable architecture. However, mismatch between current sources limits the performance of DAC. Large-area current source arrays can maintain a required level of matching accuracy between current sources, but the parasitic effect of large device results in degradation of dynamic range for high-frequency signal. So we present a new foreground self-calibration structure to overcome the problem. The calibration technique doesn't need addition high resolution analog-to-digital converter (ADC), it would reduce the complexity for circuit design. Beside, we use a deglitch technique to reduce glitch effect at switching time.
In this thesis, a 14-bit 100MS/s current-steering DAC with a low cost self-calibration structure has been implemented. It uses the above foreground self-calibration technique to overcome the mismatch between current sources, and reduce device size to decrease in degradation of dynamic range for high-frequency signal. This not only makes cost down (smaller die area) but also improves the performance of the circuit. The DAC occupies 0.99 mm2 0f active area in TSMC 0.18-um 1P6M mixed signal CMOS process. It operates in 1.8 V power supply, and the power consumption is 32mW.

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