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研究生： 孔德潔
Kung, Te-Chieh
論文名稱： 循環式類比數位轉換器之設計及線性度測試
The Design and Linearity Testing of Cyclic A/D Converters
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2008
畢業學年度： 96
語文別： 英文
論文頁數： 120
中文關鍵詞： 循環式類比數位轉換器 、線性度測試 、無輸出負載技巧 、特徵觀察測試方法 、放大器共享技術
外文關鍵詞： cyclic A/D converter, Opamp-sharing, loading free, linearity testing, characteristic observation method
相關次數： 點閱：141  下載：10 
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    • 循環式類比數位轉換器具備可在小面積內完成高解析度轉換的優點。然而、一方面由於需要數個循環才能完成一次完整的轉換，另一方面因為放大器的電容負載必須夠大以降低kT/C雜訊與不匹配誤差，因此、傳統之高解析度循環式類比數位轉換器在操作速度上相當受限。本論文提出一個低功率高速循環式類比數位轉換器的設計，其結合運算放大器共享技術以及無輸出負載技巧達到提昇電路操作速度並且降低其功率消耗。本論文使用台積電0.13微米互補式金氧半導體製程，設計一個十位元循環式類比數位轉換器，佈局後的模擬顯示，在1.2伏特的操作電壓，與每秒取樣二十萬次的操作速度下，其有效位元數為9.3位元，功率消耗為8mW，核心電路的面積為0.76mm x 0.68 mm。
    此外，在高解析度類比數位轉換器的線性度測試中，使用傳統以直方圖為基礎之測試方法將花費相當冗長之測試時間。在本論文中，針對循環式及管線式類比數位轉換器的線性度測試，提出一個特徵觀察測試方法。藉由觀察循環式及管線式類比數位轉換器之電路特性，歸納出簡化線性度測試的方法，使用此法將可大大的減少類比數位轉換器在做線性度測試時需耗費的時間。

    Cyclic analog-to-digital (A/D) converters have the advantage of requiring small silicon area to accomplish high-resolution data conversions. However, the operating speed of a high-resolution cyclic A/D converter is significantly limited because it needs several iterations to complete one data conversion and the loading capacitors of employed amplifiers should be large enough for reducing kT/C noises and mismatch errors. The first part of this thesis presents a low-power high-speed cyclic A/D converter. Opamp-sharing and loading free techniques are manipulated in the design to improve the operating speed while suppressing the power consumption. A 10-bit cyclic A/D converter using TSMC 0.13-m 1P8M CMOS process is designed in this thesis. Post-layout simulation results show that the effective number of bits and power consumption are 9.3 and 8mW respectively, under 1.2V supply voltage and 20MSamples/sec operation speed. The core area of the presented A/D converter is 0.76 mm  0.68 mm.
    Moreover, using the conventional histogram-based method for the linearity testing of high resolution A/D converter is very time-consuming because a huge number of samples have to be acquired and processed. In the second part of this thesis, a characteristic observation method is proposed for the linearity testing of cyclic/pipelined A/D converters. By observing the basic transfer characteristics of pipelined/cyclic A/D converters, only a few code bin widths, which are sufficient for accurately estimating INL/DNL performance, should be measured. Consequently, the testing time can then be reduced substantially.

    Contents V List of Tables VIII List of Figures IX Chapter 1 Introduction 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 Chapter 2 Analog-to-Digital Converter 5 2.1 A/D CONVERTER PERFORMANCE METRICS 5 2.1.1 RESOLUTION 5 2.1.2 OFFSET ERROR 6 2.1.3 GAIN ERROR 7 2.1.4 NONLINEARITY 7 2.1.5 ACCURACY 8 2.1.6 SIGNAL-TO-NOISE RATIO 9 2.1.7 SIGNAL-TO-NOISE AND DISTORTION RATIO 11 2.2 ADC ARCHITECTURES 12 2.2.1 FLASH A/D CONVERTER 12 2.2.2 TWO-STEP A/D CONVERTER 14 2.2.3 PIPELINED A/D CONVERTER 16 2.2.4 CYCLIC A/D CONVERTER 18 2.2.5 SUCCESSIVE-APPROXIMATION A/D CONVERTER 19 2.2.6 COMPARISON BETWEEN DIFFERENT A/D CONVERTER ARCHITECTURES 20 Chapter 3 The Basics of Cyclic A/D Converter and the SC Circuit 22 3.1 BASIC PRINCIPLE OF CYCLIC A/D CONVERTER 22 3.1.1 THE BASIC OPERATION OF CYCLIC A/D CONVERTER 23 3.1.2 DIGITAL ERROR CORRECTION TECHNIQUE 25 3.1.3 1.5-BIT/STAGE ARCHITECTURE 30 3.1.4 RATIO-INDEPENDENT CYCLIC A/D CONVERTER 32 3.2 STAGE RESOLUTION CONSIDERATION 34 3.2.1 STAGE RESOLUTION – 2.5-BIT/STAGE ARCHITECTURE 35 3.3 OPAMP SHARING TECHNIQUE 37 3.4 LOADING-FREE TECHNIQUE 40 3.4.1 LIMITATIONS OF THE LOADING-FREE TECHNIQUE 42 3.4.1.1 THE OPAMP SHOULD BE RESET 43 3.4.1.2 THE ARCHITECTURE WITH SMALLER FEEDBACK FACTOR 44 3.4.2 LOADING-FREE TECHNIQUE EMPLOYED IN THE CYCLIC A/D CONVERTER 45 3.5 SUMMARY 48 Chapter 4 49 Implementation of the Proposed Cyclic A/D Converter 49 4.1 A NOVEL CYCLIC A/D CONVERTER USING 2.5BIT/STAGE ARCHITECTURE WITH OPAMP SHARING AND LOADING-FREE TECHNIQUE 49 4.2 STAGE ACCURACY REQUIREMENT 53 4.2.1 ACCURACY REQUIREMENT OF THE CYCLIC A/D CONVERTER 53 4.2.2 SPECIFY CAPACITOR VALUE IN SWITCHED-CAPACITOR CIRCUITS 55 4.2.3 SPECIFY OP-AMP SPECIFICATIONS 58 4.3 CIRCUIT DESIGN AND IMPLEMENTATION 60 4.3.1 OPERATIONAL AMPLIFIER 60 4.3.1.1 ARCHITECTURE SELECTION 61 4.3.1.2 COMMON MODE FEEDBACK 64 4.3.1.3 BIAS CIRCUIT 65 4.3.1.4 SIMULATION RESULTS OF THE OPAMP 66 4.3.2 MDAC 67 4.3.3 BOOTSTRAPPED SWITCH 69 4.3.4 COMPARATOR & SUB-ADC 71 4.3.5 CLOCK GENERATOR 72 4.3.5.1 NON-OVERLAP CLOCK GENERATOR 72 4.3.5.2 PHASE SHIFTER 74 4.3.6 SYNCHRONIZED CIRCUIT AND DIGITAL ERROR CORRECTION 76 4.4 SIMULATION RESULT 76 4.5 FLOOR PLAN & LAYOUT 78 4.6 SUMMARY 80 Chapter 5 81 Linearity Testing of Pipelined and Cyclic Analog-to-Digital Converters 81 5.1 HISTOGRAM-BASED TESTING METHOD 82 5.2 THE PREVIOUS WORKS OF REDUCED-CODE BASED TESTING 84 5.2.1 NONLINEARITY-SYSTEM-ID BASED ADC LINEARITY TESTING[10] 84 5.2.2 LINEARITY-SYSTEM-ID BASED ADC LINEARITY TESTING[40] 86 5.3 THE BACKGROUND OF THE PROPOSED METHOD 87 5.3.1 ARCHITECTURE SELECTION 88 5.3.2 THE MAJOR LINEARITY ERRORS IN THE A/D CONVERTERS 88 5.4 THE PROPOSED CHARACTERISTIC OBSERVATION METHOD USED IN PIPELINED A/D CONVERTER 89 5.4.1 PIPELINED A/D CONVERTER WITH CAPACITOR MISMATCH 90 5.4.2 PIPELINED A/D CONVERTER WITH FINITE OPAMP GAIN ERROR 95 5.4.3 PIPELINED A/D CONVERTER WITH CAPACITOR MISMATCH AND FINITE OPAMP GAIN ERROR 98 5.4.4 PIPELINED A/D CONVERTER WITH GAIN ERROR AND COMPARATOR OFFSET 100 5.4.5 NON-IDEAL BEHAVIOR OF THE FIRST-TWO PIPELINED-STAGES 102 5.4.6 EFFECTIVE LINEARITY TEST CODES FOR PIPELINED A/D CONVERTERS 107 5.5 SIMULATION RESULT FOR PIPELINED A/D CONVERTERS 109 5.6 THE PROPOSED METHOD USED IN CYCLIC A/D CONVERTERS 111 5.7 SUMMARY 113 Chapter 6 114 Conclusion and Future Work 114 6.1 CONCLUSION 114 6.2 FUTURE WORK 115 BIBLIOGRAPHY 116

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