電流驅動式數位類比轉換器具有能直接驅動外面負載的特性，故被廣泛使用於高速的應用上，但此種電流驅動式數位類比會遭受到製程上元件不匹配效應，此種效應會同時限制轉換器的靜態與動態線性度，在本篇論文中提出一個新型校正架構來改善其元件不匹配效應所造成的影響，另外，非線性的輸出轉換也會同樣降低其動態效能，最近幾年當中，在非線性的輸出時間中常會利用輸出歸零技巧將輸出歸零來改善其效能，但這同樣損失了一半輸出能量在歸零上，在此也提出一種固定時間歸零技巧來使改善其動態效能之餘，也不致於會浪費過多的能量在歸零時間上。
　　我們將在這次論文中實現一個十四位元電流驅動式數位類比轉換器，它使用上述的自我校正架構與固定時間歸零機制來改善其靜態及動態上的效能，它採用1P6M CMOS製程，其整體面積是1.07mm x 1.07mm，在模擬中INL與DNL期望小於0.5 LSB，在200-MHz的操作頻率下，低輸出頻率下，其SFDR可達到77dB，高輸出頻率下，其SFDR可達到68dB，在1.8V的電源供應下，其功率損耗是43mW，在量測上其INL是3.66LSB，其SFDR在20-MHz操作頻率下，在信號頻率超過3-MHz之前都能保持大於60 dB。

　Current-Steering Digital-to-Analog Converters (DACs) can directly drive external loads and are commonly used for high-speed application. However, these current-steering DACs suffer from the element mismatch of technologies and this limit both the static and dynamic linearity. In this thesis, a new calibration structure to improve the element mismatch is presented. Besides, the nonlinear transient output also degrades the dynamic performance. Recently, the return-to-zero method is used to attenuate the output when this nonlinear transient occurs, but loses half of output power, too. Here, we also propose a fixed-time return-to-zero scheme to improve the dynamic performance without losing much output power.
　A 14-bit 200-MHz current-steering DAC is implemented in this thesis. It uses the above self-calibration circuit to obtain the static linearity and fixed-time return-to-zero output to obtain the dynamic linearity. The DAC occupies 1.07mm X 1.07 mm in a 0.18-um 1P6M CMOS process. In the simulation, the INL and DNL is expected to be less than 0.5 LSB and the SFDR is 77dB at the lower output frequency and 68dB at the high output frequency when this DAC operates at the design clock of 200MS/s. It consumes 43mW from a 1.8V supply. In the measurement, the INL is 3.66LSB and the SFDR remains above 60 dB up to a signal frequency of 3-MHz at the update rate of 20 MS/s.

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