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研究生: 游日亨
You, Ze-Hen
論文名稱: 可撓式塑膠基板上利用熱鎢絲化學氣相低溫沉積製作奈米晶矽薄膜電晶體研究
The Study of Nanocrystalline Silicon Thin Film Transistor on Flexible Plastic Substrate by Hot-Wire Chemical Vapor Deposition
指導教授: 方炎坤
Fang, Yean-Kuen
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2008
畢業學年度: 96
語文別: 中文
論文頁數: 121
中文關鍵詞: 奈米晶矽薄膜熱鎢絲化學氣象低溫沉積聚碳酸酯聚醯亞胺可撓式塑膠基板
外文關鍵詞: Polyimide, Polycarbonate, Nanocrystalline Silicon Thin Film, Hot-Wire Chemical Vapor Deposition, Flexible Plastic Substrate
相關次數: 點閱:92下載:5
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  • 本論文結合了可撓式塑膠基板、奈米晶矽薄膜和熱鎢絲化學氣相低溫沉積,製作可撓式奈米晶矽薄膜電晶體。可撓式塑膠基板具有外型輕薄、價格便宜且可彎曲的特質。奈米矽晶薄膜特性介於多晶矽(poly-Si)與非晶矽(a-Si)之間,可低溫下(<250℃)大面積沉積,其不但具有非晶矽薄膜的製程簡單,大面積成長的優點,且具有多晶矽薄膜的高遷移率及驅動電流大的優勢。熱鎢絲化學氣相沉積法則是成長速率高(6.5nm/min),製程簡單。
    吾人利用聚碳酸酯(polycarbonate)和聚醯亞胺(polyimide)兩種可撓式基板材料,並研究不同製程,如將阻隔層平坦化,降低製成溫度(225℃)、縮短反應距離(4.5cm)和反應時間,製作奈米晶矽薄膜。並以場發射掃瞄式電子顯微鏡(FESEM)、原子力顯微鏡(AFM)檢測奈米晶矽薄膜表面形態,和用HP4145半導體參數分析儀,量測薄膜導電特性。結果發現聚醯亞胺基板較適合製作電晶體。以聚醯亞胺基板製作的可撓式奈米晶矽薄膜晶體,其開關電流比為1.16×103、場效遷移率為4.3(cm2/Vs)、臨界電壓為17.88伏特。這些結果不但堪與奈米晶矽薄膜晶體製作在傳統玻璃或矽基板上相比,而且較佳於傳統製作在玻璃基板上非晶矽電晶體。

    In the thesis, we studied and optimized the different growing parameters such as using planarization barrier oxide, depositing temperature, and the distance between tungsten wire heater and substrate, and deposition time to prepare the nanocrystalline silicon thin films (nc-Si) on flexible plastic substrate by hot-wire chemical vapor deposition system (HWCVD). Both polycarbonate(PC) and polyimide(PI) were chosen as the flexible plastic substrate. The HW-CVD was adopted for its high deposition rate (6.5nm/min). Then, based on the optimized parameter, the nc-Si thin film transistors (nc-Si TFTs) were developed also on flexible plastic substrate. The nc-Si thin film has higher mobility and driving current than that of amorphous Si (a-Si) film, and can be uniformly deposited at low temperature (250℃). The film’s quality was examined with AFM and FESEM and I-V curve. The examination found the PI substrate is better for fabrication ns-Si TFT than the PC counterpart.
    The ns-Si TFT on PI substrate, has current ratio of 1.16×103, drift mobility of 4.3(cm2/Vs), and the threshold voltage of 17.88(volt). These data are comparable to the ns-Si TFT on traditional Si or glass substrate, but are better than that of a-Si TFT on glass substrate.

    目錄 中文摘要 ………………………………………………I 英文摘要 ……………………………………………III 目錄 ……………………………………………………V 圖表目錄………………………………………………IX 第一章 導論 1-1 前言 1 1-2 可撓式顯示器基板類型 2 1-3 薄膜電晶體(thin film transistor,TFT) 3 1-4 奈米晶矽(nanocrystal silicon,nc-Si) 5 1-5 論文架構 6 第二章 塑膠基板材質簡介 2-1 工程塑膠 8 2-2 PET聚對苯二甲酸乙酯 10 2-3 PEN萘二甲酸乙二酯 10 2-4 PES聚醚碸 11 2-5 PI聚醯亞胺 11 2-6 PC聚碳酸酯 12 第三章 薄膜電晶體工作原理及構造 3-1薄膜電晶體基本結構 14 3-2薄膜電晶體工作原理 14 3-2-1 汲極電流相對於汲極電壓的I-V曲線 14 3-2-2 汲極電流相對於閘極電壓的I-V曲線 16 3-3薄膜電晶體電性參數 18 第四章 製程量測儀器與實驗步驟介紹 4-1 HWCVD特性 22 4-2 影響奈米晶矽薄膜的參數 25 4-3 TFT相關製程技術 30 4-3-1 真空蒸著系統 30 4-3-2 射頻磁控濺鍍系統 31 4-3-3 紫外光臭氧清洗機 33 4-4量測儀器 33 4-4-1 場放射型掃描式電子顯微鏡 33 4-4-2 原子力顯微鏡 34 4-4-3 α-step 膜厚量測儀 35 4-4-4 HP4145B半導體參數分析儀 35 4-5實驗製程步驟 35 4-5-1 可撓式奈米晶矽薄膜製作步驟 36 4-5-2 PI基板可撓式奈米晶矽薄膜電晶體製作步驟 39 第五章 可撓式元件成果及特性討論 5-1 利用PC聚碳酸酯基板成長可撓式奈米晶矽薄膜分析 42 5-1-1 利用二氧化矽阻隔層在PC基板上成長奈米晶矽42 5-1-2 二氧化矽阻隔層臭氧平坦化處理 43 5-1-3 利用疊層技術改善PC基板奈米晶矽薄膜 45 5-2 利用PI聚醯亞胺基板成長可撓式奈米晶矽薄膜分析 46 5-2-1 利用PI基板成長奈米晶矽薄膜 46 5-2-2 反應距離與PI基板上奈米晶矽薄膜特性分析 48 5-2-3 成長時間與PI基板上奈米晶矽薄膜特性分析 50 5-2-4 矽基板與PI基板上奈米晶矽薄膜比較 51 5-3 利用PI基板製作可撓式奈米晶矽薄膜電晶體 52 5-3-1 開關電流比(ON/OFF ratio) 53 5-3-2場效遷移率(field effect mobility、μfet) 53 5-3-3 臨界電壓(Threshold voltage、VT) 53 5-3-4 次臨限擺幅(Subthreshold Swing、SS) 54 5-3-5 總結 54 第六章 結論與展望 6-1 結論 56 6-2 展望 58 Reference 59

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