| 研究生: |
蘇偉棠 Su, Wei-Tang |
|---|---|
| 論文名稱: |
三角積分類比數位轉換器之低功率數位濾波器晶片之研製 The design of low power decimation filter chip for Sigma-Delta converter |
| 指導教授: |
羅錦興
Luo, Ching-Hsing |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2006 |
| 畢業學年度: | 94 |
| 語文別: | 中文 |
| 論文頁數: | 94 |
| 中文關鍵詞: | 三角積分 、降頻濾波器 、低功率 |
| 外文關鍵詞: | Sigma Delta, low power, decimation filter |
| 相關次數: | 點閱:84 下載:3 |
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本論文旨在實現一個適切效能、低電壓、低耗能的三角積分類比/數位轉換器,將原本大家熟知最佔面積、最耗電的數位濾波器部份加以改善,並成功將其實現,往後有利生物晶片計劃的整合,本晶片可進一步配合其他生醫系統,如心電圖、肌電圖、腦波圖、血壓計、遠距診斷系統,做即時的生理信號監視,可使生醫遙測系統更加完整。
另外,根據本論文所介紹設計方法,一個適用於三角積分類比/數位轉換器已經成功被設計完成,其中較為創新的方法是製作適用本研究室其他同學所設計的轉換器規格來修改Sinc filter的架構,並採用低功率的流程及方法來設計後四級的FIR filter,因此在效能上已比先前的設計更為提升;然而我使用聯電0.18μm、1P6M的數位製程及Artisan UMC0.18μm cell library來製作本晶片, 2006年2月前瞻性晶片於CIC中心成功下線,晶片編號為UMC18-95A-03a,經模擬及測試後的結果得知,本晶片具有十二位元的解析度(Resolution)可處理三角積分類比/數位轉換器,晶片支援最快速度可達100MHz。
In the study, we would like to realize an efficient and low power consuming Sigma Delta A/D converters (SDADCs). For the reason we need to improve the digital filter part is that mostly area required and power consumed part we have known for decades. As long as we complete the design for the chip, further integration of bio-chips will be greatly boosted. Nevertheless, the chip is able to be used within bio-systems such as cardio graphic, ergo graph, brain wave, blood pressure, remote diagnose and supervision. Otherwise, we can get the physical signals of the patients. Hence it will make our bio-medical remote supervising system more intact.
In addition, regarding the method offered in the thesis, the design of the digital filter for SDADCs has already been fabricated. An innovative idea is to adapt the structure of the sinc filter within the low power filter in order to achieve the goals of low power consumption and to fit, my previous stage, the Sigma Delta A/D modulator in our lab. Furthermore, the low power design flow and method were implemented to designs of following FIR filter stages. Consequently, the performance was greatly lifted comparing to earlier designs in the lab. Moreover, the UMC 0.18 μm, 1P6M process and Artisan UMC 0.18 μm cell library were used for chip fabrication. Besides, the chip was tapped out to CIC with a serial number “UMC18-95A-03a” in February 2006. Refer to the simulation and measurements, the resolution for SDADCs can achieve 12 bits. What is more, the maximum operating frequency of the chip is 100MHz.
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