| 研究生: |
王師涵 Wang, Shi-Han |
|---|---|
| 論文名稱: |
應用雙空腔結構設計提升熱電能源採集器效能之研究 Development of a Thermoelectric Energy Generator with Double Cavity Design by Standard CMOS Process for Higher Performance |
| 指導教授: |
楊世銘
Yang, Shih-Ming |
| 學位類別: |
碩士 Master |
| 系所名稱: |
工學院 - 航空太空工程學系 Department of Aeronautics & Astronautics |
| 論文出版年: | 2019 |
| 畢業學年度: | 107 |
| 語文別: | 英文 |
| 論文頁數: | 65 |
| 中文關鍵詞: | 熱電能源轉換器 、CMOS 製程 、雙空腔設計 、晶圓級真空封裝 |
| 外文關鍵詞: | Thermoelectric energy generator chip, CMOS process, Double cavity design, Wafer level vacuum packaging |
| 相關次數: | 點閱:111 下載:5 |
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熱電能源轉換器可以將裝置的熱端與冷端之間的溫差藉由Seebeck effect轉換為電能輸出。本研究提出擁有雙空腔設計之熱電能源轉換晶片並利用 TSMC D35 互補式金屬氧化物半導體製程設計與製作,接著利用後製程蝕刻出5.2 μm的上空腔以及10 μm的下空腔,雙空腔設計可以提升熱電能源轉換器晶片的性能並減少後製程時間。量測結果顯示,擁有雙空腔設計之熱電能源轉換器晶片在面積為2 mm × 2 mm下,其voltage factor為2.889 mV/cm2K;power factor為0.0450 μW/cm2K2;電阻為7.2 MΩ,相較於只有下空腔設計之熱電能源轉換晶片提升了20%之性能。除此之外,本研究提出晶圓級真空封裝方法以提供熱電能源轉換晶片保護並提升熱隔絕空腔之效用。
A thermoelectric energy generator (TEG) is to convert temperature difference between the hot and cold junctions into electric energy by Seebeck effect. This thesis proposes a TEG chip with double cavity design by TSMC D35 CMOS standard process. The double cavity design with upper cavity 5.2 μm and lower cavity 10 μm by post process is shown to improve TEG performance and reduce process time. Measurement result shows that the 2 mm × 2 mm TEG chip has voltage factor 2.889 V/cm2K and power factor 0.0450 μW/cm2K2 under 7.2 MΩ resistance, which is 20% higher than the TEG chip only with lower cavity in the previous work. In addition, wafer level packaging in vacuum is proposed for the TEG chip to improve thermal isolation for circuit and device integration.
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校內:2022-09-18公開