本篇論文提出一個具備綠能設計概念之遞迴式離散傅立業轉換(Recursive Discrete Fourier Transform, RDFT)架構，此架構具有高產量、節能、免記憶元件及可重新組態化等優點。並以RDFT為核心架構拓展出修正型離散餘弦正轉換(Modified Discrete Cosine Transform, MDCT)及其逆轉換(Inverse Modified Discrete Cosine Transform, IMDCT)，達到硬體資源共享，大大地降低硬體實現成本，此為綠能設計理念之一。
由於傳統RDFT架構運算速度過慢，為彌補速度上之限制，所提出之架構將會採取2-D形式之演算法來加以提升。本架構與最新Lai et al. RDFT[40]比較，其運算所需週期降低49.53%，在乘、加運算方面，加法運算量改善為原設計的53.03%、乘法運算量改善為原設計的53.60%。 除此之外，此架構還具有4倍之DTPT (Data Throughput per Transformation, DTPT)，達成低複雜度、低功耗之綠能設計構想。
最後，我們將此架構規劃運用於數位全球無線電廣播(Digital Radio Mondiale, DRM)系統上，該系統不僅運用到DFT運算(規格點數N=288、256、176、112)，也因其採用MPGE-4 HE-AAC作為DRM音訊編解碼，故MDCT/IMDCT之運算(規格點數N=1920、240)勢必不可或缺。因此，對於一個可攜式的DRM接收器而言，如何有效的設計共架構之DFT與IMDCT實為一個重要的議題。我們藉此系統來驗證所提出之RDFT架構及以RDFT為核心之MDCT/IMDCT架構的效能，並在本論文中作各種遞迴架構之分析討論。
所提之架構電路，利用TSMC 0.18µm 1P6M COMS製程實現，其核心面積為0.84x0.84 mm2，操作頻率為25MHz之下所測得平均功耗為14.6mW。因此，此設計能較有效率及較為合適被運用於DRM系統上。

This thesis presents a green design of fast recursive discrete Fourier transform (RDFT) architecture. The advantages of the proposed design include high-throughput, power-efficient, memory-free and more reconfigurable. This thesis also discuss the issue of applying this RDFT design to Modified Discrete Cosine Transform (MDCT) and Inverse Modified Discrete Cosine Transform (IMDCT), which results in an improvement of hardware-sharing and achieves lower-cost.
To improve the lack-of-efficiency problem in traditional RDFT architecture, the 2-D architecture algorithm is used in our design. Compared with the latest RDFT architecture proposed by Lai et al, 49.53% reduction of the overall clock cycles is presented in our design; and the computational amount of multiplication and addition presented are reduced to 53.60% and 53.03% of Lai’s design. In addition, the proposed architecture holds four times of DTPT (Data Throughput per Transformation, DTPT) than the traditional architecture; which achieves our goal of presenting a low complexity and low power-cost design.
Furthermore, this architecture is applied on Digital Radio Mondiale (DRM) system in our design. Not only DFT computation(288、256、176、112 point) but MPGE-4 HE-AAC techniques are applied on DRM audio coding(1920、240 point). Therefore, to design a common architecture of DFT and IMDCT becomes an important issue for portable DRM receiver. This system is used to examine the performance of the RDFT architecture which we proposed in the front text as well as to discuss other architectures in this article.
Moreover, this RDFT processor is implemented by using TSMC 0.18µm 1P6M CMOS technology. The core size is 0.84x0.84mm2 and the power consummation is 14.6mW@25MHz. To conclude, the proposed design would be more efficient and more suitable for DRM applications than previous works.

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