近年來，AI 人工智慧領域快速發展，深度學習模型越來越龐大，對於運算硬體 的要求也越來越高，而在人工智慧領域中有一些應用則是需要在終端進行實時(Real- time)的運算。本實驗室開發的 CASLab-GPU 為一個通用型的繪圖處理器(General Purpose GPU)，在本實驗室開發的軟體支援下，可以在終端有效率的執行許多深度學習 的模型。
目前本實驗室開發的 CASLab-GPU 為一個使用電子系統層級設計技術(Electronic System Level, ESL)設計的 SystemC 模型。雖然 CASLab-GPU 中大部分的硬體模組設計 為 cycle accurate，但目前除錯系統的硬體設計並非 cycle accurate，而是利用 C++語言的 指標完成資料的傳輸，沒有明確定義硬體模組之間的接線和設計。另外目前設計方法並 沒有辦法做 High Level Synthesis，因此要做合成之前還需要依照目前 SystemC 模型設計 出相對應的 RTL 層級的模型。
因此，在本論文中，針對除錯系統設計及規劃了硬體模組的細節。在除錯系統中， 詳細規劃了 Hardware information、profiler，以及 interrupt handling 的硬體設計，包括硬 體模組間的訊號線溝通及資料寬度。另外，為了新的硬體設計，也重新定義了一些可供 軟體讀寫的 register。因此本論文在軟體端，包括 CASLab-GDB、Linux Device Driver， 以及 OpenCL Runtime 都有做相對應的修改，以支援和重新規劃的硬體溝通，並且實作 interrupt handling 的機制。

As the rapid growth of the field of Artificial Intelligence, the Deep Learning models require fast and complex computing unit. CASLab has been developing a general-purpose GPU, CASLab-GPU, for accelerating edge computation of deep learning models. With the software support, lots of modern deep learning models have already been deployed and executed on CASLab-GPU.
The CASLab-GPU model was designed at Electronic System Level by SystemC language. Although most of the modules in CASLab-GPU were cycle-accurate, the debug system in CASLab-GPU was only a behavior model. The data transmission of debug system was implemented by pointer in C++ language. In this case, detailed hardware design of the debug system including I/O interface, addressable registers and wire connection were necessary for the implementation of the RTL model in the future.
This thesis described the details of hardware module design in the debug system. Hardware information, profiler, and interrupt handling were introduced in the hardware design. To support the new hardware design in this thesis, the changes in the software including CASLab-GDB, Linux Device Driver, and OpenCL runtime were also introduced.

[1] Yu-Ting Chu, “Design of Debugger Framework for CASLab-GPU Platform”, the thesis for Master of Science. National Cheng Kung University, Tainan, Taiwan. 2021.
[2] Bellard, F.. “QEMU, a Fast and Portable Dynamic Translator,” USENIX Annual Technical Conference, FREENIX Track (2005).
[3] Sheng-Yang Hung, “Virtual Platform Design of Acceleration based on RISC-V Architecture with CASLab-GPU”, the thesis for Master of Science. National Cheng Kung University, Tainan, Taiwan. 2021.
[4]“SystemC Official Website” [online], available:
https://systemc.org/.
[5] RISC-V Foundation, “RISC-V: The Free and Open RISC Instruction Set Architecture”, https://riscv.org/
[6] HSA Foundation. “Heterogeneous System Architecture,” http://www.hsafoundation.com/.
[7] Khronos OpenCL Working Group, “The OpenCL Specification,” https://www.khronos.org/registry/OpenCL/specs/opencl-1.2.pdf