本研究提出了一系列支援語音控制任務的高效率解決方案，在其中針對的語音控制任務包含了語音識別、語者識別、非待選詞彙偵測、以及非待測語者偵測。這一系列改善的研究涉及了三個層級—演算法層級(ECWRT, CWCWRT, BHC, two-stage out-of-vocabulary detection method, and statistical based out-of-speaker detection method)、電路架構層級 (ULQAB, ERT core, MFSR, CPE, and MRC)、以及系統層級。通過應用這些方法，本研究應用所提出來的改善方法，並實現在四個不同的語音控制系統來作為效能評估。
第一個系統中, ULQAB方法與ECWRT方法被使用在嵌入式語音辨識系統的實現中。此系統被實現在一個16位元微處理器平台（GPCE063A）上，工作時脈為49.152MHZ，信號取樣為8kHz;本系統的實驗展示了在30個待選詞彙中，該平台達到95.22％的辨識率，僅使用0.75kB的系統記憶體。
第二個系統中，語者獨立的語音辨識系統以積體電路的形式被設計。為了達到低成本的晶片設計目的，ULQAB被應用來在記憶體受到限制的規格下實現語音特徵值計算。與沒有採用ULQAB技術的系統相比，在自相關計算中，本系統可節省96.48%的記憶體需求以及256倍的系統回應速度(256 sample/frame 的系統中)。此外，改善的LPCC特徵值萃取計算有效的應用在其最佳化的電路設計並降低被專門設計的電路面積運算需求以及關鍵路徑。這個晶片透過國家晶片中心（CIC）以台灣積體電路公司所提供的90nm製成實現。晶片面積1.16x1.16mm2, 48-pin封裝，採用了43,609個邏輯閘，10MHz的工作時脈，支援8kH的信號取樣率。
第三個系統，非待選語者(OOS)非待選詞彙(OOV)偵測演算法被提出，並包含語音語者辨識(ASSR)實作在FPGA平台中。此語音語者辨識系統包含四個部分 – 1)信號預處理模組，2)語者模型訓練模組，3)語者語音辨識模組，以及4) 非待選語者與非待選詞彙偵測模組。本工作提出的非待選語者演算法克服了傳統方法需要預先訓練背景模型來加強分辨非參與使用者的缺點。此OOS偵測演算法被整合至或者說是緊密的嵌入至本研究提出的語者分類方法(Binary Halved Clustering,BHC)中，為語者辨識器增加了非待選語者識別效能。在此系統的實驗中指出，此系統可達到87.3%的語者辨識率以及86.6%的語音辨識率。而在非待語者與非待選詞彙的實驗中，分別達到88.3% 及 80.5%的識別率。此系統所採用的FPGA平台為ALTERA DE2-70，設定的工作時脈在50MHz, 並僅僅使用了13,355個邏輯單元以及40.41K bytes記憶體用量。
第四個系統為基於extraction, recognition, and training (ERT) 之處理單元設計之語音語者辨識系統的積體電路設計。對於積體電路系統的設計，硬體的成本以及運算的時間複雜度總是重要的議題，在本工作重兩個層級(包含演算法層級以及電路架構層級)上予以討論。在演算法層級提出了binary-halved clustering (BHC) 以降低運算的時間複雜度以及記憶體需求。而在硬體架構層級，基於運算所需的資料相關分析以及硬體重複利用率考量下提出了extraction, recognition, and training (ERT) 處理核心，利用此核心可良好的降低系統運算時間以及電路成本。本系統基於台積電提供之TSMC 90 nm製程技術經過合成元件擺放佈線等程序完成晶片設計。為了測量整合後BHC演算法帶給系統之效能改善，本工作執行了9位語者模型訓練的模擬工作。此外，在辨識功能上，系統也在語音以語者辨識兩個部份執行了模擬，並分別可達到93.38% 及 87.56% 的辨識率。本系統之積體電路設計使用了396 k gate counts平均功耗為8.74 mW。與相關系統進行比較後的結果指出，本系統優於傳統相關功能的系統。

This study proposes a series of solutions to achieve the high efficient way in voice control tasks (including speech recognition, speaker recognition, out-of-vocabulary detection, and out-of-speaker detection tasks). Three levels of improvement are involved in this study which including — algorithm level (ECWRT, CWCWRT, BHC, two-stage out-of-vocabulary detection method, and statistical based out-of-speaker detection method), architecture level (ULQAB, ERT core, MFSR, CPE, and MRC), as well as system level. Applying the proposed methods, four type of voice control systems are implemented.
In the first system, the Ultra-Low Queue-Accumulator Buffering (ULQAB) method and the Enhanced Cross-Words Reference Templates (ECWRT) are adopted for an implementation of embedded auto-speech recognition (ASR) system. This system is implemented on a 16-bit microprocessor GPCE063A platform with a 49.152 MHz clock, using a sampling rate of 8 kHz. Experimental results demonstrate that recognition accuracy reaches 95.22% in a 30-sentence speaker-independent embedded ASR task, using only 0.75 kB RAM.
In the second system, speaker-independent ASR system is implemented in a Chip. To achieve a low cost chip design, the ULQAB method is applied to realize the feature extraction operation in limited memory resources. Totally, 96.48% of memory requirement of auto-correlation computation can be reduced and the response time of the autocorrelation computation for one frame can be performed 256 times improvement. Besides, the improved linear prediction cepstral coefficients (LPCC) feature extraction procedure and its related optimized circuits reduce the dedicated hardware area, computational requirements, and the critical path. This study has been taped-out in TSMC’s 90nm process via Chip Implementation Center (CIC). The chip area is 1.16×1.16 mm2, 48-pin package, gate count is 43609, and the power dissipation is 1.006 mW. The operation frequency is 10 MHz, while the Sampling rate is 4 kHz.
In third system, an Out-of-Speaker (OOS) and an Out-of-Vocabulary (OOV) detection algorithm are proposed and implemented an Automatic Speaker-Speech Recognition (ASSR) system on a FPGA platform. The ASSR system includes four parts: 1) pre-processing, 2) speaker model training, 3) speaker and speech recognition and 4) OOS & OOV detection. The proposed OOS algorithm overcomes the drawback of the traditional method trained in the Universal Background Model (UBM) to verify the unrolled speaker in the training models. The proposed novel OOS detection is thereafter embedded Binary Halved Clustering (BHC) based ASSR system to improve the target and unrolled speakers recognition performance. The experimental results indicate that the proposed work can achieve 87.3% and 86.7% of speaker and speech recognition rate, respectively. The OOS and OOV detection rate can reach to 88.3% and 80.5%, respectively. This system is implemented on ALTERA DE2-70 under 50MHz working frequency, and the total counts of utilized logic element is only 13355 and the memory usage is only 40.41K bytes.
The fourth work presents an automatic speech speaker recognition (ASSR) system implemented in a chip which includes a built-in extraction, recognition, and training (ERT) core. For VLSI design (here ASSR system), the hardware cost and time complexity are always the important issues which are improved in this design in two levels ― Algorithmic and architecture. At the algorithm level, a newly binary-halved clustering (BHC) is proposed to achieve low time complexity and low memory requirement. Besides, at the architecture level, a new ERT core is proposed and implemented based on data dependency and reuse mechanism to reduce the time and hardware cost as well. Finally, the chip implementation is synthesized, placed, and routed by using TSMC 90 nm technology library. To verify the performance of the proposed BHC method, a case study is performed based on nine speakers. Moreover, the validation of the ASSR system is examined in two parts ― speech and speaker recognition. The results show that the proposed system can achieve the 93.38% and 87.56% of recognition rates during speech and speaker recognition, respectively. Furthermore, the proposed ASSR chip includes 396 k gate counts, and consumes power in 8.74 mW. Such results demonstrate that the performance of the proposed ASSR system is superior to the conventional systems.

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