簡易檢索 / 詳目顯示

回結果列表
研究生： 林郁傑
Lin, Yu-Chieh
論文名稱： 先進匯流排協定之嵌入式高效能匯流排設計
High Performance On-Chip Bus Design for Advanced Bus Protocols
指導教授： 李昆忠
Lee, Kuen-Jong
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2011
畢業學年度： 99
語文別： 英文
論文頁數： 64
中文關鍵詞： bus 、pipelined 、out-of-order
外文關鍵詞： 匯流排, 平行運算, 不須依序
相關次數： 點閱：53  下載：0 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 對於單晶片系統的整體效能，嵌入式匯流排扮演著一個很重要的角色，用來增加匯流排效率的先進匯流排協定如開放核心協定與AXI已經被提出。在這篇論文我們發展了可以處理先進匯流排功能的傳輸包含爆發(Burst)模式、多筆平行運算、不須依序(Out-of-order)寫入傳輸及不須依序(Out-of-order)讀取傳輸的高效能嵌入式匯流排設計。特別地，我們發展了兩種方法去處理匯流排在支援不須依序傳輸時所發生的死結問題。我們將這些設計應用到開放核心協定和AXI之後，去評估我們提出匯流排設計的效能及所需要的硬體成本。和一些之前的著作比較，實驗結果顯示我們的匯流排設計所需要的硬體成本是可以接受的，而且可以降低傳輸所需要的時間。

    On-chip buses play an important role in the overall performance of SOC designs. Advanced bus protocols such as OCP and AXI to enhance the bus efficiency have been proposed to improve the efficiency of on-chip buses. In this work we develop high-performance on-chip bus design that can deal with most advanced bus functionalities, including burst, pipelined, WR out-of-order and RD out-of-order transactions. In particular, we develop two methods to deal with the deadlock problem that may occur when a bus supports out-of-order transactions. To evaluate the performance and hardware cost of our proposed design, we apply it to both OCP and AXI protocols. Experimental results show that our bus design requires acceptable hardware cost compared to some previous work and can reduce the communication time.

    CHAPTER 1 INTRODUCTION 1 1.1 Motivations 1 1.2 Overview of This Work 2 1.3 Thesis Organization 3 CHAPTER 2 BACKGROUND AND PREVIOUS WORK 5 2.1 Open Core Protocol (OCP) 5 2.2 Advanced Bus Functionalities 7 2.2.1 Burst Transactions 8 2.2.2 Pipelined (Outstanding) Transactions 8 2.2.3 WR Out-of-Order Transactions 9 2.2.4 RD Out-of-Order Transactions 10 2.3 Out-of-Order Deadlock 11 2.4 Previous Work 13 2.4.1 On-Chip Bus Design 13 2.4.2 The Deadlock Solutions of ARM 15 CHAPTER 3 IN-ORDER BUS ARCHITECTURE 18 3.1 Overview of the In-order Bus Architecture 18 3.2 Detailed Descriptions 19 3.2.1 Decoder 19 3.2.2 Request Busy Checker (Request BC) 20 3.2.3 WR/RD Recorder 21 3.2.4 Arbiter 21 3.2.5 WR/RD In-Order Access Controller 22 CHAPTER 4 OUT-OF-ORDER BUS ARCHITECTURE 24 4.1 Out-of-order Bus Architecture without Deadlock Solutions 24 4.1.1 Request Buffer 25 4.1.2 Data Buffer 26 4.1.3 Response Buffer 26 4.1.4 WR/RD Out-of-Order Access Controller 27 4.2 Out-of-order Bus Architecture with Deadlock Avoidance 28 4.3 Out-of-order Bus Architecture with Combination of Deadlock Avoidance/Untying 29 CHAPTER 5 HARDWARE IMPLEMENTATION OF DEADLOCK AVOIDANCE AND COMBINATION OF DEADLOCK AVOIDANCE/UNTYING 32 5.1 Deadlock Solutions 32 5.2 Deadlock Avoidance 34 5.2.1 Waiting Relationship Detector 37 5.2.2 Deadlock Avoider 40 5.2.3 The Cases of Unsafe States 42 5.3 Combination of Deadlock Avoidance/Untying 47 5.3.1 DLAU Buffer Size Checker 48 5.3.2 DLAU Buffer 52 CHAPTER 6 EXPERIMENTAL RESULTS 54 6.1 Performance Analysis and Hardware Cost of the Proposed Bus Design 54 6.2 Performance Comparisons of Deadlock Solutions 56 6.3 Area Overhead of Deadlock Avoidance and Combination of Deadlock Avoidance/Untying 58 CHAPTER 7 CONCLUSIONS 61 REFERENCES 62

    [1] S. Dutta, R. Jensen, and A. Rieckmann, “Viper: A Multiprocessor SoC for Advanced Set-Top Box and Digital TV Systems,” IEEE Design and Test of Computers, vol. 18, no. 5, pp. 21-31, Sept./Oct. 2001.
    [2] Intel. Product Brief: Intel IXP2850 Network Processor, http://www.intel.com/design/network/prodbrf/25213601.pdf, Jan. 2009.
    [3] STMicroelectronics, Nomadik Open Multimedia Platform for Next-Generation Mobile Devices, http://www.st.com/stonline/books/ascii/docs/9306.htm, Jan. 2009.
    [4] Texas Instruments OMAP, http://www.omap.com, Jan. 2009.
    [5] Tilera Corp. TILE64 Processor Family, http://www.tilera.com/products/processors.php, Jan. 2009.
    [6] Advanced Microcontroller Bus Architecture (AMBA) Specification Rev 2.0 & 3.0, http://www.arm.com.
    [7] Open Core Protocol specification. Available: http://www.ocpip.org/
    [8] K. Lahiri, A. Raghunathan, and G. Lakshminarayana, “The LOTTERYBUS on-chip communication architecture,” IEEE Trans. on Very Large Scale Integration System, vol. 14, no. 6, pp. 596-608, 2006.
    [9] Multi-Layer AHB, http://www.arm.com.
    [10] S.H. Chitra, and A. Kandaswamy, "A high performance on-chip segmented bus architecture using dynamic bridge-by-pass technique," in Proc. International Conference on Industrial and Information Systems (ICIIS), pp. 249-254, 2010.
    [11] K. Lahiri, A. Raghunathan, and S. Dey, “Design of high-performance system-on-chips using communication architecture tuners,rfIEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 5, pp. 919-932, 2004.
    [12] K. Sekar, K. Lahiri, A. Raghunathan, and S. Dey, "Dynamically configurable bus topologies for high-performance on-chip communication," IEEE Trans. on Very Large Scale Integration System, vol. 16, no. 10, pp. 1413-1426, 2008.
    [13] S. Malik and X. Zhu, “A hierarchical modeling framework for on-chip communication architectures,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 663-670, 2002.
    [14] O. Ogawa, S. Bayon de Noyer, P. Chauvet, K. Shinohara, Y. Watanabe, H. Niizuma, T. Sasaki, and Y. Takai, “A practical approach for bus architecture optimization at transaction level,” Design, Automation, and Test in Europe, pp. 176-181, 2003.
    [15] M. Caldari, M. Conti, M. Coppola, S. Curaba, L. Pieralisi, and C. Turchetti, “Transaction-level models for AMBA bus architecture using SystemC 2.0,” Design, Automation, and Test in Europe, pp. 26-31, 2003.
    [16] Y.-T. Kim, T. Kim, Y. Kim, C. Shin, E.-Y. Chung, K.-M. Choi, J.-T. Kong, and S.-K. Eo, “Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture,” Design, Automation, and Test in Europe, pp. 138-139, 2005.
    [17] G. Schirner and R. Domer, “Quantitative Analysis of Transaction Level Models for the AMBA Bus,” Design, Automation, and Test in Europe, pp. 1-6, 2006.
    [18] C.-K. Lo and R.-S. Tsay, “Automatic Generation of Cycle Accurate and Cycle Count Accurate Transaction Level Bus Models from a Formal Model,” Asia and South Pacific Design Automation Conference, pp. 558-563, 2009.
    [19] S. Pasricha, D. Nikil, and M. Ben-Romdhane, “Extending the transaction level modeling approach for fast communication architecture exploration,” in Proc. Design Automation Conf., pp. 113-118, 2004.
    [20] N.Y.-C. Chang, Y.-Z. Liao and T.-S. Chang, “Analysis of Shared-link AXI,” IET Computers & Digital Techniques, vol. 3, pp. 373-383, 2009.
    [21] F. M. Xiao, D. S. Li. G. M. Du, Y. K. Song, D. L. Zhang and M. L. Gao, “Design of AXI bus based MPSoC on FPGA,” Anti-counterfeiting, Security, and Identification in Communication, pp. 560-564, 2009.
    [22] H. W. Wang, C. S. Lai, C. F. Wu, S. A. Hwang, and Y. H. Lin, “On-chip Interconnection Design and SoC Integration with OCP,” in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test, pp. 25-28, 2008.
    [23] PrimeCell AXI Configurable Interconnect (PL300) Technical Reference Manual, http://www.arm.comL. Cai and D. Gajski, “Transaction level modeling: an overview,” in Proc. First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp. 19-24, 2003.

    無法下載圖示 校內：2016-08-05公開
    校外：不公開
    電子論文尚未授權公開，紙本請查館藏目錄
    QR CODE