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研究生：	廖翊博 Liao, Yi-Bo
論文名稱：	高密度之全包覆式閘極電晶體設計 High-Density Gate-All-Around CMOS Design
指導教授：	許渭州 Hsu, Wei-Chou
共同指導教授:	江孟學 Chiang, Meng-Hsueh
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 微電子工程研究所 Institute of Microelectronics
論文出版年：	2014
畢業學年度：	102
語文別：	英文
論文頁數：	93
中文關鍵詞：	鰭式電晶體、包覆式閘極電晶體、堆疊式結構、6T-SRAM
外文關鍵詞：	SOI/Bulk FinFET, Gate-all-around (GAA) MOSFETs, Stack wire structure, 6T-SRAM
相關次數：	點閱：118 下載：12
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傳統單閘極的電晶體結構，在半導體製程技術微縮至22 nm技術節點下，已被多閘極結構的鰭式電晶體所取代，由於多閘極電晶體擁有更佳的通道控制能力，因此，電晶體的漏電流更容易被抑制，電晶體在次臨界區的次臨界擺幅能有更良好特性，然而，電晶體為了能被更進一步的微縮，使用完全包覆式閘極結構，已被視為是在電晶體被微縮至10 nm尺寸後的最佳解決方案，擁有通道被完全包覆的結構，能使得電晶體閘極控制能力更優於鰭式電晶體，本論文分別探討鰭式電晶體與完全包覆式閘極電晶體之特性。
本論文利用三維數值模擬軟體，在10 nm的電晶體閘極尺寸，分別針對鰭式電晶體和完全包覆式閘極電晶體進行分析。通常鰭式電晶體被製作於SOI基板上，然而，使用傳統的bulk-Si基板將有助於成本的降低，但是會造成電晶體漏電流的大量增加，本篇論文針對於不同抑制漏電流之方法進行設計的最佳化，並提出堆疊式閘極結構來解決鰭式電晶體製造於bulk-Si基板的漏電流問題，其漏電流由10-6 A下降至10-9 A與SOI相同，此外，使用堆疊式閘極結構也有效的降低離散摻質對臨界電壓的影響。
在完全包覆式電晶體結構方面，傳統結構與無接面結構皆在此論文討論，因為製程變異而造成非理想的尺寸變化，其變異對電晶體特性的影響也在本論文中討論，其中包含通道尺寸及臨界電壓的變異，而臨界電壓的變異是由離散摻質、閘極線寬粗糙及金屬功函數變異所造成，在考慮上述之製程變異因素，其6T-SRAM電路之良率及特性影響皆在本論文被討論，相較於傳統設計，在最佳化的設計後，其6T-SRAM將可有效的減少28%的佈局面積。
為了實現高密度及低功率消耗的應用，使用堆疊式的包覆式閘極電晶體結構，除了可保有良好的電晶體特性外，並可以提升電晶體密度，另外，為了實現SoC的應用，如何完成多階臨界電壓的設計將是一個重要的課題，本論文利用不同摻質濃度的堆疊式結構，完成多階臨界電壓的調整，並保有高輸出電流之特性，本論文亦提出有效摻質濃度及堆疊數量的設計方法及數學模型，以提供元件與電路設計者使用。

This dissertation presents a device design methodology for the gate-all-around (GAA) MOSFETs with a focus on high-density VLSI application. The non-planar GAA MOSFETs relieve the physical device scaling limitations while the technology roadmap is moving towards sub-10 nm regime. Since the drive current of the non-planar device can not be arbitrarily set by the channel width as for the conventional planar MOSFETs and instead it is achieved by a multi-fin configuration, a new design methodology is needed to ensure area efficiency. Relying on the physical insight to the unique gate-to-gate coupling in the GAA structure, high-density SRAM design methodology with optimized device structure is proposed using three-dimensional TCAD simulation and a calibrated macro model.
Another multi-gate structure – FinFET has been involved in mass production since 22 nm technology. FinFETs are generally non-planar and are fabricated on SOI wafers. Alternatively, feasibility of using bulk-Si wafer is being sought for productivity and cost of wafers and more importantly for the compatibility with bulk CMOS technology. However, the substrate leakage current underneath the channel requires additional isolation oxide and substrate doping for its suppression. In this dissertation, the thickness of isolation oxide and concentration of substrate doping are investigated and optimized. A new device structure – stacked-gate FinFET is also proposed in order to resolve the leakage current issue (from 10-6 A to 10-9A) without additional substrate doping.
Two types of GAA MOSFETs in inversion and junctionless (JL) modes are discussed. A novel 6T-SRAM design with the pass-gate transistors replaced with JL MOSFTEs is provided to improve static noise margin in the same layout area. An electrostatic parameter – scale length is utilized for channel dimension design. Yield of 6T-SRAM is estimated based on channel length, width and threshold voltage variation. Random dopant fluctuations (RDFs), gate line-edge roughness (G-LER), and gate work function (WFV) are investigated for threshold voltage variation. A rectangular (thin and wide) channel design is suggested for balanced read/write yield and 28% smaller cell layout area than the double square fin design.
Multi-threshold voltage (Vt) is required for SoC application. However, how to implement such design spec in stacked GAA MOSFETs, which are developed for higher drive current purpose, is an issue; conventional gate length adjustment is not sufficient for a wide range of Vt selection. We propose a novel stacked technique with in-situ channel doping to achieve multi-threshold voltage for SoC application. The benefit and limitation of the proposed technique are investigated. An analytical threshold voltage model with effective doping concentration is provided for the design window.

摘要	I
ABSTRACT	III
誌謝	V
CONTENTS	VI
FIGURE CAPTIONS	X
TABLE CAPTIONS	XVI
CHAPTER 1	INTRODUCTION	1
1-1	BACKGROUND AND MOTIVATION	1
1-2	MULTI-GATE MOSFETS	2
1-2-1	FinFETs	2
1-2-2	Gate-all-around (GAA) MOSFETs	2
1-3	OVERVIEW OF THE DISSERTATION	3
CHAPTER 2	FINFET DEVICE DESIGN	4
2-1	OPTIMAL DEVICE DESIGN OF FINFETS ON A BULK SUBSTRATE	4
2-1-1	SOI and Bulk-Si FinFET Design	4
2-1-1-1	Device Structure and Numerical Simulation Methodology	4
2-1-1-2	Bulk FinFET Conceptual Process	6
2-1-2	Leakage Current Suppression Schemes	7
2-1-2-1	Design with Undoped Silicon Substrate and Various Isolation Thickness	8
2-1-2-2	Design with Doped Silicon Substrate and Various Isolation Thickness	10
2-1-3	Optimal Design and Design Window Estimation	12
2-1-3-1	Optimal Design	12
2-1-3-2	Design Window Estimation	13
2-2	STACK-GATE FINFET TECHNIQUE FOR DOPINGLESS BULK FINFET	15
2-2-1	Bulk-Si FinFET with Gaussian Doping Profile	16
2-2-1-1	Device Structure and Simulation Methodology	16
2-2-1-2	Leakage Current Issue and Suppression Approaches	16
2-2-2	Stack-Gate Technique	19
2-2-2-1	Stack-Gate Structure and Conceptual Process	19
2-2-2-2	Stack-Gate with Ploysilicon Gate	20
2-2-2-3	Stack-Gate with Metal Gate	21
2-2-3	Design Insight and Design Methodology	23
2-2-3-1	Design Insight in Gate Work Function	23
2-2-3-2	Impact of Random Dopant Fluctuations (RDFs)	26
2-3	SUMMARY	28
2-3-1	Summary of Bulk FinFET	28
2-3-2	Comparison of FinFET and Gate-all-around MOSFET	29
CHAPTER 3	GATE-ALL-AROUND (GAA) MOSFETS AND APPLICATION	30
3-1	DEVICE STRUCTURE VARIATION	30
3-1-1	Nominal Device Structure	30
3-1-2	Non-ideal Structure	32
3-2	A NOVEL 6T-SRAM DESIGN	33
3-2-1	6T-SRAM Design with Junctionless NW	34
3-2-2	Reduced Area	36
3-3	CIRCUIT VARIABILITY ASSESSMENT	37
3-3-1	Impacts of Variation in Conventional 6T-SRAM Design	37
3-3-2	Impacts of Variation in Novel 6T-SRAM Design	38
3-3-3	Comparison and Discussion	39
3-4	SUMMARY	41
CHAPTER 4	GAA SRAM DESIGN AND YIELD ESTIMATION	42
4-1	GAA MOSFETS DESIGN AND OPTIMIZATION	42
4-1-1	Scale Length (λ)	43
4-1-2	Optimization of Channel Region Dimensions	44
4-1-3	Compact Model	48
4-2	GAA 6T-SRAM DESIGN	50
4-2-1	Read Static Noise Margin and Write-ability Current	50
4-2-2	Design Optimization	52
4-2-3	Cell Area Comparison	53
4-3	GAA 6T-SRAM CELL YIELD ESTIMATION	54
4-3-1	Impact of Random Variation	55
4-3-2	SRAM Cell Yield Estimation	57
4-4	SUMMARY	60
CHAPTER 5	STACKED-WIRE GAA DESIGN	61
5-1	STACK-WIRE GAA MOSFETS	61
5-1-1	Device Structure and Simulation Methodology	61
5-1-2	Conceptual Process of Stacked Wires	62
5-1-3	Choice of Stack Number	63
5-2	DESIGN METHODOLOGY FOR SOC APPLICATION	65
5-2-1	Threshold Voltage Adjustment	65
5-2-2	Multi-channel Doping in Stack-Wire Structure	67
5-3	THRESHOLD VOLTAGE ANALYSIS AND MODELING	68
5-3-1	Insight of Threshold Voltage (Vt)	68
5-3-2	Analytical Model of Effective Concentration (NA,eff)	70
5-3-3	Analytical Modeling of Vt	71
5-3-4	Design Methodology	73
5-4	CHANNEL LENGTH ADJUSTMENT	75
5-5	SUMMARY	76
CHAPTER 6	CONCLUSION	78
6-1	SUGGESTED FUTURE WORK	79
REFERENCES	80
APPENDIX 1 ANALYTICAL MOSFET MODEL	88
VITA	91
PUBLICATION LIST OF YI-BO LIAO	92

                                    

[1] L. Geppert, “The amazing vanishing transistor act,” IEEE Spectrum, Otc. 2002.
[2] R. Nathanael, W. Xiong, C. R. Cleavelin, and T.-J. King Liu, “Impact of gate0induced strain on MuGFET reliability,” IEEE Electron Device Letters, vol. 29, pp. 916-919, 2008.
[3] C.-H. Lin, R. Kambhampati, R. J. Miller, T. B. Hook, A. Bryant, W. Haensch et al., “Channel doping impact on FinFETs for 22nm and beyond,” in Proc. VLSI Symp. Tech., pp. 15-16, 2012.
[4] S. Bangsaruntip, G. M. Cohen, A. Majumdar, Y. Zhang, S. U. Engelmann,N. C. M. Fuller, L. M. Gignac, S. Mittal, J. S. Newbury, M. Guillorn, T. Barwicz, L. Sekaric, M. M. Frank, and J. W. Sleight, “High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling,” in IEDM Tech. Dig., pp. 12.3.1-12.3.2, 2009.
[5] B. Yang, K. D. Buddharaju, S. H. G. Teo, N. Singh, G. Q. Lo, and D. L. Kwong, “Vertical silicon-nanowire formation and gate-all-around MOSFET,” IEEE Electron Device Letters, vol. 29, pp. 791-794, 2008.
[6] S. C. Rustagi, N. Singh, W. W. Fang, K. D. Buddharaju, S. R. Omampuliyur, S. H. G. Teo, C. H Tung, G. Q. Lo, N. Baalasubramanian, and D. L. Kwong, “CMOS inverter based on gate-all-around silicon-nanowire MOSFETs fabricated using top-down approach,” IEEE Electron Device Letters, vol. 28, pp, 1021-1024, 2007.
[7] J. T. Park, and J.-P. Colinge, “Multiple-gate SOI MOSFETs: device design guidelines,” IEEE Trans. on Electron Devices, vol. 49, pp. 2222-2229, 2002.
[8] D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, “FinFET-a self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Trans. on Electron Device, vol. 47, pp. 2320-2325, 2000.
[9] Y.-K. Choi, T.-J. King, and C. Hu, “A spacer patterning technology for nanoscale CMOS,” IEEE Trans. on Electron Devices, vol. 49, pp. 436-441, 2002.
[10] S. Takagi, T. Irisawa, T. Tezuka, T. Numata, S. Nakaharai, N. Hirashita, Y. Moriyama, K. Usuda, E. Toyoda, S. Dissanayake, M. Shichijo, R. Nakane, S. Sugahara, M. Takenaka, and N. Sugiyama, “Carrier-transport-enhanced channel CMOS for improved power consumption and performance,” IEEE Trans. on Electron Device, vol. 55, pp. 21-39, 2008.
[11] J. G. Fossum, Z. Zhou, L. Mathew, and B.-Y. Nguyen, “SOI versus bulk-silicon nanoscale FinFETs,” Solid-State Electron, vol. 54, pp. 86-89, 2010.
[12] M. Nauaz, S. Decker, L.-F. Giles, W. Molzer, and T. Schulz, “Evaluation of process parameter space of bulk FinFET using 3D TCAD,” Microelectronic Engineering, vol. 85, pp. 1529-1539, 2008.
[13] M. Poljak, V. Jovanovic, and T. Suligoj, “Improving bulk FinFET DC performance in comparison to SOI FinFET,” Microelectronic Engineering, vol. 86, pp. 2078-2085, 2009.
[14] International Technology Roadmap for Semiconductors, 2007~2011 (Online: http://public.itrs.net/)
[15] Taurus-Device ver: X-2005.10, User Guide Synopsys Inc., Oct. 2005
[16] M. Poljak, V. Jovanovic, and T. Suligoj, “Modeling study on carrier mobility in ultra-thin body FinFETs with circuit-level implications,” Solid-State Electronics, vol. 65-66, pp. 130-138, 2011.
[17] K. Uchida. H. Watanabe, A. Kinoshita. J. Koga, T. Numata, and S. Takagi, “Experimental study on carrier transport mechanism in ultrathin-body SOI n- and p-MOSFETs with SOI thickness less than 5 nm,” in IEDM Tech. Dig., pp. 47-50, 2002.
[18] G. Tsutsui, M. Saitoh, T. Saraya, T. Nagumo, and T. Hiramoto, “Mobility enhancement due to volume inversion in (100)-oriented ultra-thin body double-gate nMOSFETs with body thickness less than 5 nm,” in IEDM Tech. Dig., pp. 729-732, 2005.
[19] C. C. Wu, D. W. Lin, A. Keshavarzi, C. H. Huang, C. T. Chan, C. H. Tseng, C. L. Chen, C. Y. Hsieh, K. Y. Wong, M. L. Cheng, T. H. Li, Y. C. Lin, L. Y. Yang, C. P. Lin, C. S. Hou, H. C. Ling, J. L. Yang, K. F. Yu, M. J. Chen, T. H. Hsieh, Y. C. Peng, C. H. Chou, C. J. Lee, C. W. Huang, C. Y. Lu, F. K. Yang, H. K. Chen, L. W. Weng, P. C. Yen, S. H. Wang, S. W. Chang, S. W. Chuang, T. C. Gan, T. L. Wu, T. Y. Lee, W. S. Huang, Y. J. Huang, Y. W. Tseng, C. M. Wu, Eric Ou-Yang, K. Y. Hsu, L. T. Lin, S. B. Wang, T. M. Kwok, C. C. Su, C. H. Tsai, M. J. Huang, M. H. Lin, A. S. Chang, S. H. Liao, L. S. Chen, J. H. Chen, P. S. Lim, X. F. Yu, S. Y. Ku, Y. B. Lee, P. C. Hsieh, P. W. Wang, Y. H. Chiu. S. S. Lin, H. J. Tao, M. Cao, and Y. J. Mii, “High performance 22/20nm FinFET CMOS devices with advance high-k/metal gate scheme,” in IEDM Tech. Dig., pp. 27.1.1-27.1.4, 2010.
[20] D. Shamiryan, A. Redolfi, and W. Boullart, “Dry etching process for bulk FinFET manufacturing,” Microelectronic Engineering, vol. 86, pp. 96-98, 2009.
[21] K. Okano, T. Izumida, H. Kawasaki, A. Kaneko, A. Yagishita, T. Kanemura, M. Kondo, S. Ito, N. Aoki, K. Miyano, T. Ono*, K. Yahashi, K. Iwade, T. Kubota, T. Matsushita, I. Mizushima, S. Inaba, K. Ishimaru, K. Suguro, K. Eguchi, Y. Tsunashima, and H. Ishiuchi, “Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with subg-10 nm Fin width and 20 nm gate length,” in IEDM Tech. Dig., pp. 721-724, 2005.
[22] C. R Manoj. M. Nagpal, D. Varghese, and V. R. Rao, “Device design and optimization considerations for bulk FinFETs,” IEEE Trans. on Electron Devices, vol. 55, pp. 609-615, 2008.
[23] Sentaurus User’s Manual, Synopsys Inc. ver. G-2012.06, June 2012.
[24] C. Auth C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, R. Grover, W. Han, D. Hanken, M. Hattendorf, P. Hentges, R. Heussner, J. Hicks, D. Ingerly, P. Jain, S. Jaloviar, R. James, D. Jones, J. Jopling, S. Joshi, C. Kenyon, H. Liu, R. McFadden, B. McIntyre, J. Neirynck, C. Parker, L. Pipes, I. Post, S. Pradhan, M. Prince, S. Ramey, T. Reynolds, J. Roesler, J. Sandford. J. Seiple, P. Smith, C. Thomas, D. Towner, T. Troeger, C. Weber, P. Yashar, K. Zawadzki, and K. Mistry, “A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contact and high density MIM capacitors,” in Proc. VLSI Symp. Tech., pp. 131-132, 2012.
[25] C. Auth, A. Cappellani, J.-S. Chun, A. Dalis, A. Davis, T. Ghani, G. Glass, T. Glassman, M. Harper, M. Hattendorf, P. Hentges, S. Jaloviar, S. Joshi, J. Klaus, K. Kuhn, D. Lavric, M. Lu, H. Mariappan, K. Mistry, B. Norris, N. Rahhal-orabi, P. Ranade, J. Sandford, L. Shifren, V. Souw, K. Tone, F. Tambwe, A. Thompson, D. Towner, T. Troeger, P. Vandervoorn, C. Wallace, J. Wiedemer, C. Wiegand, “45nm high-k + metal gate strain-enhanced transistors,” in Proc. VLSI Symp. Tech., pp. 128-129, 2008.
[26] V. Narayanan, V. K. Paruchuri, N. A. Bojarczuk, B. P. Linder, B.Doris, Y. H. Kim, S. Zafar, J. Stathis, S. Brown, J.Arnold, , M. Copel, M. Steen, E. Cartier, A. Callegari, P. Jamison, J. -P. Locquet1, D. L. Lacey, Y. Wang, P. E. Batson, P. Ronsheim, R. Jammy, M. P. Chudzik, M. Ieong, S. Guha, G. Shahidi, and T. C. Chen, “Band-edge high-performance high-k/metal gate n-MOSFETs using cap layers containing group IIA and IIIB elements with gate-first processing for 45 nm and beyond,” in Proc. VLSI Symp. Tech., pp. 178-179, 2006.
[27] K. Choi, H. Jagannathan, C. Choi, L. Edge, T. Ando, M. Frank, P. Jamison, M. Wang, E. Cartier, S. Zafar, J. Bruley, A. Kerber, B. Linder, A. Callegari, Q. Yang, S. Brown, J. Stathis, J. Iacoponi, V. Paruchuri, and V. Narayanan, “Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22nm technology node and beyond,” in Proc. VLSI Symp. Tech., pp. 138-139, 2009.
[28] H. F. Dadgour, K. Endo, V. K. De, K. Banerjee, “Grain-orientation induced work function variation in nanoscale metal-gate transistors-part I: modeling, analysis, and experimental validation,” IEEE Trans. Electron Devices, vol. 57, no. 10, pp. 2504-2514, 2010.
[29] A. Martinez, M. Aldegunde, N. Seoane, A. R. Brown, J. R. Barker, and A. Asenov, “Quantum-transport study on the impact of channel length and cross sections on variability induced by random discrete dopants in narrow gate-all-around silicon nanowire transistors,” IEEE Trans. Electron Devices, vol. 58, no. 8, pp. 2209-2217, 2011.
[30] V. Vidya, L. Smith, and T.-J. King Liu, “FinFET design for tolerance to statistical dopant fluctuations,” IEEE Trans. Nanotechnology, vol. 8, no. 3, pp. 375-378, 2009.
[31] W. Lu, P. Xie, and C. M. Lieber, “Nanowire transistor performance limits and applications,” IEEE Trans. on Electron Devices, vol. 55, pp. 2859-2876, 2008.
[32] J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistor without junctions,” Nature Nanotechnology, vol. 5, pp. 225-229, 2010.
[33] Y. Wu, Y. Cui, L. Huynh, C. J. Barrelet, D. C. Bell, and C. M. Lieber, “Controlled growth and structures of molecular-scale silicon nanowires,” Nano Letters, vol. 4, pp. 433-436, 2004.
[34] N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, “High-performance fully depleted silicon nanowire (diameter <= 5 nm) gate-all-around CMOS devices,” IEEE Electron Device Letters, vol. 27, pp. 383-386, 2006.
[35] P. Hashemi, J. T. Teherani, and J. L. Hoyt, “Investigation of hole mobility in gate-all-around Si nanowire p-MOSFETs with high-k/metal-gate: effects of hydrogen thermal annealing and nanowire shape,” in IEDM Tech. Dig., pp.34.5.1-34.5.4, 2010.
[36] K. Kim, J. B. Kuang, F. H. Gebara, H. C. Ngo, C.-T. Chuang, and K. J. Nowka, “TCAD/physics-based analysis of high-density dual-BOX FD/SOI SRAM cell,” IEEE Trans. on Electron Devices, vol. 56, pp. 3033-3040, 2009.
[37] A. Kranti, C.-W. Lee, I. Ferain, R. Yan, N. Akhavan, R. Razavi, R. Yu, G. A. Armstrong, and J.-P. Colinge, “Junctionless 6T SRAM cell,” IEEE Electron Letter, vol. 46, pp. 1491-1493, 2010.
[38] A. Asenov, “Simulation of statistical variability in nano MOSFETs,” in VLSI Symp. Tech. Dig., pp. 86–87, 2007.
[39] C. Shin, M. H. Cho, Y. Tsukamoto, B.-Y. Nguyen, C. Mazure, B. Nikolic, and T.-J. King Liu, “Performance and area scaling benefits of FD-SOI technology for 6-T SRAM cells at the 22-nm node,” IEEE Transactions on Electron Devices, vol. 57, pp. 1301-1309, 2010.
[40] C. Shin, N. Damrongplasit, X, Sun, Y. Tsukamoto, B. Nikolic, and T.-J. King Liu, “Performance and yield benefits of quasi-planar bulk CMOS technology for 6-T SRAM at the 22-nm node,” IEEE Transactions on Electron Devices, vol. 28, pp. 1846-1854, 2011.
[41] N. Damrongplasit, N. Xu, H. Takeuchi, R. J. Stephenson, N. W. Cody, A. Yiptong, X. Huang, M. Hytha, R. J. Mears, and T.-J. King Liu, “Comparative study of uniform versus supersteep retrograde MOSFET channel doping and implications for 6-T SRAM yield,” IEEE Transactions on Electron Devices, vol. 60, pp. 1790-1793, 2013.
[42] R.-H. Yan, A. Ourmazd, and K. F. Lee, “Scaling the Si MOSFETS: from bulk to SOI to bulk,” IEEE Transactions on Electron Devices, vol. 39, pp. 17041710, 1992.
[43] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, “Scaling theory for double-gate SOI MOSFET’s,” IEEE Transactions on Electron Devices, vol. 40, pp. 2326-2329, 1993.
[44] C. P. Auth, and J. D. Plummer, “Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET’s,” IEEE Electron Device Letters, vol. 18, pp. 74-76, 1997.
[45] S. Bangsaruntip, G. M. Cohen, A. Majumdar, and J. W. Sleight, “Universality of short-channel effects in undoped-body silicon nanowire MOSFETs,” IEEE Electron Device Letters, vol. 31, pp. 903-905, 2010.
[46] A. Hokazono, K. Ohuchi, K. Miyano, I. Mizushima, Y. Tsunashima, and Y. Toyoshima, “Source/drain engineering for sub-100nm CMOS using selective epitaxial growth technique,” in IEDM Tech. Dig., pp. 243-246, 2000.
[47] V. Varadarajan, Ph.D. dissertation, Dept. EECS Univ. California Berkeley, Berkeley, CA, pp. 40-69, 2001.
[48] A. E. Carlson, “Device and circuit techniques for reducing variation in nanoscale SRAM,” Ph. D. dissertation, Dept. EECS Univ. California Berkeley, Berkeley, CA, pp. 21-61, 2008.
[49] C. Shin, “Advanced MOSFET designs and implications for SRAM scaling,” Ph. D. dissertation, Dep. EECS Univ. California Berkeley, Berkeley, CA, pp. 23-37, 2011.
[50] A. Asenov, S. Kaya, and A. R. Brown, “Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness,” IEEE Transactions on Electron Devices, vol. 50, pp.1254-1260, 2003.
[51] H. Dadgour, K. Endo, V. De, and K. Banerjee, “Modeling and analysis of grain-orientation effects in emerging metal-gate devices and implications for SRAM reliability,” in IEDM Tech. Dig., pp. 705-708, 2008.
[52] X. Wang, B. Cheng, A. R. Brown, C. Millar, and A. Asenov, “Statistical variability in 14-nm node SOI FinFETs and its impact on corresponding 6T-SRAM cell design,” in Proc. ESSDERC, pp. 113-116, 2012.
[53] T. Ernst, C. Dupre, C. Isheden, E. Bernard, R. Ritzenthaler, V. Maffini-Alvaro, et al., “Novel 3D integration process for highly scalable nano-beam stacked-channel GAA (NBG) FinFET with HfO2/TiN gate stack,” in IEDM Tech. Dig., pp. 1-4, 2006.
[54] C. Dupre, A. Hubert, S. Becu, M. Jublot, V. Maffini-Alvaro, C. Vizioz, et al., “15nm-dimeter 3D stacked nanowire with independent gate operation: ΦFET,” in IEDM Tech. Dig., pp. 1-4, 2008.
[55] C. Dupre, T. Ernst, V. Maffini-Alvaro, V. Delaye, J.-M. hartmann, S. Borel, C. Vizioz, O. Faynot, G. Ghibaudo, and S. Deleonibus, “3D nanowire gate-all-around transistors: specific integration and electrical features,” Solid-State Electronics, vol. 52, pp. 519-525, 2008.
[56] S. Bangsaruntip, K. Balakrishnan, S.-L. Cheng, J. Chang, M. Brink, I. Lauer, et al., “Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond,” in IEDM Tech. Dig., pp. 20.2.1-20.2.4, 2013.
[57] A. Hubert, E. Nowak, K. Tachi, V. Maffini-Alvaro, C. Vizioz, C. Arvet, et al., “A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with gate-all-around or independent gate (Φ-Flash), suitable for full 3D integration,” in IEDM Tech. Dig., pp. 1-4, 2009.

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