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研究生: 尤祥安
You, Hsiang-An
論文名稱: 低資料相依性之高基數管線腓特比解碼器之運算單元設計
Design of High-Radix Pipelined Add_Compare _Select Unit with Low Data Dependency for Viterbi Decoders
指導教授: 謝明得
Shieh, Ming-Der
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2005
畢業學年度: 93
語文別: 英文
論文頁數: 55
中文關鍵詞: 腓特比解碼器迴旋碼高基數管線
外文關鍵詞: Viterbi decoder, Convolutional codes, High radix pipelined
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  •   在數位通訊系統下廣泛地使用迴旋碼,由於它們有極好的錯誤修正效能。在高速度腓特比解碼器(VD)的實現上,如何有效縮減路徑計量值記憶體(PMMU)並搭配運算單元間連線複雜度,和如何提高運算單元(ACSU loop)間管線級數,已成為實現高速度VD的關鍵技術。在本論文,首先為了縮減連線的複雜度,我們提出一個全新且有效的定位模式(Extended In-Place)技術,可使得記憶體區塊與運算單元(ACSU)間接線方式為單一且直接之區域化(locally)形式。然後為了增加運算單元間管線級數,我們提出一個可降低資料相依性的系統化重排(Reorder)演算法。在本論文發展的架構有下列特性: (1) 記憶體可以有系統的分割成多個獨立的區塊, (2)記憶體區塊可以合併成固定數量虛擬記憶體區塊。這將不只大幅降低位址產生電路的面積且有效的降低記憶體面積,(3) 根據所提的重排(reorder)演算法及實驗結果,可證明我們管線架構的級數達到近似重排(reorder)技術的最佳情況。

      Convolutional codes are widely used in communication systems due to their excellent error-control performance. High-speed Viterbi decoders for convolutional codes are of great interest for high data-rate applications. How to reduce the interconnection network efficiently between the path metric memory unit (PMMU) and add_compare_select unit(ACSU), and how to increase the pipelined stage within the loop of ACSU are always the key techniques for successfully designing the high- speed Viterbi decoders. In this thesis, In order to reduce the interconnect overhead further, we first present a novel and efficient in-place scheduling technique, denoted as the extended in-place scheduling, such that every ACSU will only access a dedicated, partitioned memory bank; therefore, the interconnection network is simplified and the bank becomes local to the specific ACSU conceptually. After that, in order to increase the pipelined stages of ACSU, we present a systematic reordering algorithm to relax the data dependences among consecutive trellis stages. The result architecture has the following characteristics: (1) The whole memory can be systematically partition into several sets of banks and each set can be treated as local memory of a specific ACSU. (2) The partitioned memory banks can be merged into a fixed number of pseudo-banks regardless of the number of ACS operations. (3) Based on the presented reordering technique, more pipelined stages be come available, Experimental results also show that the performance of the proposed reordering scheme is close to that of the optimal solution and to achieve the best situation that approximate to reorder technique.

    Chapter 1 Intriduction..................................................1 1.1 Overview of ECC in the digital communication system.................1 1.2 Motivation..........................................................2 1.3 Organization of Thesis..............................................3 Chapter 2 Background and Previous Work..................................4 2.1 Convolution Code....................................................4 2.2 Viterbi Algorithm and Implementation................................6 2.3 Conventional Approach of Path Metric Update.........................9 2.4 Radix-2k Butterfly Module for Viterbi decoding......................10 2.4.1 Radix-4 Butterfly Module..........................................11 2.4.2 Radix-2k Butterfly Module.........................................12 2.5 Review of Previous Work.............................................13 2.5.1 Partition memory by mathematical formulas.........................13 2.5.2 Properties of Conflict-Free Memory Addressing Assignment..........16 2.5.3 The Conflict-Free Architectures...................................18 Chapter 3 Local Memory of Fixed Interconnection Design for High Radix...24 3.1 Novel Scheduling Methodology: Extend In-place Scheduling............24 3.1.1 The Memory Bank Routing Relationship..............................26 3.2 Conflict-Free Radix-4 Architecture..................................29 3.3 Pseudo Bank Design..................................................32 3.4 Address Generation for Radix–4 extended In-place scheduling scheme.35 Chapter 4 Reorder Technique under Viterbi Decoding......................38 4.1 Data Dependency Problem in the Viterbi Decoder......................38 4.1.1 Relationship of Butterfly-Index mapping...........................40 4.2 Solve Data Hazard Using Re-order Technique..........................45 4.2.1 Search the Optimal execution order using Re-order Technique.......46 4.2.2 Systematic Execution Order........................................47 4.3 Experimental Result and Comparison..................................51 Chapter 5 Conclusion....................................................53 5.1 Summary.............................................................53 5.2 Future work.........................................................53 Reference...............................................................54

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