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研究生: 蔡尚達
Tsai, Shang-Ta
論文名稱: 適用於H.264/AVC熵解碼器和反離散餘弦轉換之可重組化架構設計
A Reconfigurable Architecture for Entropy Decoders and IDCT in H.264/AVC
指導教授: 謝明得
Shieh, Ming-Der
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2008
畢業學年度: 96
語文別: 英文
論文頁數: 59
中文關鍵詞: 離散餘弦轉換可重組化解碼器
外文關鍵詞: idct, entropy, h.264, reconfigurable, cabac, cavlc
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  • 本論文旨在探討如何有效合併H.264/AVC所採用的內容適應性二位元算數編碼(CABAC)與內容適應性變動長度編碼(CAVLC)兩種熵編碼演算法,透過分析CABAC與CAVLC熵解碼器的異同,我們提出一個粗顆粒可重組化架構來有效率地結合CAVLC至CABAC熵解碼器中,因為相較於細顆粒可重組化架構,粗顆粒可重組化架構在特定用途的應用中有顯而易見的優勢。根據實驗結果顯示,採用可重組化元件架構後,可以節省1.5 K的邏輯閘,相當於實現一個CAVLC熵解碼器所需25.4%的硬體面積。除此之外,透過修改可重組化元件,我們只要增加相當有限的硬體面積,就可以利用可重組化元件陣列閒置的時間去執行反離散餘弦轉換,如此一來我們的設計可以在工作頻率66 MHz時即時解碼Main Profile Level 3.0條件下的串流位元影像。

    Coarse-grain reconfigurable architectures can offer obvious advantages over the fine-grain counterparts for some specific applications. This thesis explores techniques to combine the two entropy decoding methods, context-based adaptive binary arithmetic coding (CABAC) and context-based adaptive variable length coding (CAVLC), provided in H.264/AVC using the coarse-grain reconfigurable architecture. By analyzing the similarities and differences between these two decoding processes, we show how to effectively merge the CAVLC into the CABAC decoder. Experimental results exhibit that about 1.5 K gates can be saved using our reconfigurable cell (RC) architecture, which corresponds to 25.4% area savings in implementing the CAVLC decoder. To use the idle time in RC arrays, the base cell can be further extended to carry out the inverse discrete cosine transform (IDCT) with very limited overhead. In this manner, our entropy decoder design, operated in 66 MHz, can decode video sequences at Main Profile Level 3.0 under the real-time constraint.

    Chapter 1 Introduction 1 1.1 Overview of H.264/AVC 1 1.2 Introduction to Entropy Coding 3 1.3 Motivations 4 1.4 Organization of this Thesis 6 Chapter 2 Background 7 2.1 Information Theory 7 2.2 Huffman Coding Algorithm 8 2.3 Arithmetic Coding Algorithm 11 2.4 Overview of CAVLC Decoding Algorithm 12 2.5 Overview of CABAC Decoding Algorithm 14 2.5.1 Context modeler 15 2.5.2 Binary Arithmetic Decoder 18 2.5.2.1 Normal Mode 18 2.5.2.2 Bypass Mode 22 2.5.2.3 Terminal Mode 22 2.5.3 Inverse Binarization 23 2.6 IDCT and Inverse Hadamard Transform 24 Chapter 3 Proposed Architecture 26 3.1 CAVLC Decoder 26 3.2 CABAC Decoder 29 3.3 Resource Sharing Analysis 31 3.4 Syntax Element Decoding Flow 33 3.5 Distribution of mvd Bins 37 3.6 Operation Analysis 37 3.7 Proposed Reconfigurable IDCT/Entropy Decoder 38 3.7.1 4x4 Reconfigurable Cell Array 39 3.7.2 Processing Flow Analysis 40 3.7.3 Reconfigurable Cell 41 3.7.4 Memory Arrangement of MVD Memory 42 3.7.5 Data Flow and Data Path 43 Chapter 4 Experimental Results 45 4.1 System Overview and External Components 45 4.2 Synthesis Setting 46 4.3 Experimental Results and Performance Analysis 48 4.4 Verification Plan 50 4.6 I/O Pin Definitions 52 4.5 Memory Arrangements 53 Chapter 5 Conclusions and Future Work 55 5.1 Conclusions 55 5.2 Future Work 55 References 57

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