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研究生：	廖予中 Liao, Yu-Chung
論文名稱：	GSM(1.8GHz)/WLAN(2.4GHz)共存系統之鎖相迴路與一高速類比除三電路之設計 A PLL for GSM(1.8GHz)/WLAN(2.4GHz) Coexistence System and A High-Speed Analog Divide-by-Three Circuit
指導教授：	黃尊禧 Huang, Tzuen-Hsi
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	116
中文關鍵詞：	鎖相迴路、除頻器
外文關鍵詞：	Divider, PLL
相關次數：	點閱：62 下載：5
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本論文可分為兩個部份：第一部份我們設計一個整數型的
鎖相迴路，其中包含相位檢測器、電流幫浦、二階低通濾波器
、可切換式共振器的壓控振盪器與整數型Ｎ的除頻器。第二部
份中，我們設計一個類比式除三電路可應用於超寬頻頻率合成
器。
在本論文中，我們試著建構一個符合GSM/ WLAN 共存系統
的鎖相迴路，此鎖相迴路提供在GSM 與WLAN的頻帶中可鎖定所
要的頻率；另一方面，藉著將切換式電感整合到壓控振盪器中
，利用可切換式電感結構來提供可切換至GSM或WLAN 頻帶的中
心振盪頻率。利用可切換式電容陣列來提供一個較寬的可調變
頻率範圍而不會劣化相位雜訊。
本論文中我們亦實現一個除三電路。在本實驗室中，我們
提出一個應用在UWB MB-OFDＭ系統中的頻率合成器架構，此頻
率合成器所需要擁有的頻率共計有7128MHz、3168MHz、1584MH
z和528MHz等四個頻率。我們規劃利用1584 MHz除三便可產生5
28 MHz，因此除三電路在此頻率合成器中是必需的。此除三電
路中，我們是使用injection lock的方式來實現。
　　此論文的貢獻在於：第一，提出並下線製作一個GSM/WLA
N共存系統的鎖相迴路；第二，實現了一個注入鎖定除頻電路可
應用於超寬頻射頻頻率合成器。

This thesis can be divided into two major parts: In the first part, we concern about the design of an integer-N phase lock loop (PLL) including a phase-frequency detector (PFD), a charge pump (CP), a second-order low pass filter (LPF), a voltage controlled oscillator (VCO) using switched resonator, and an integer-N type of prescaler. In the second part, we design an analog divide-by-three circuit which can be applied for the UWB RF synthesizer use.
In this thesis, we try to construct a PLL for the GSM/WLAN co-existence system. Such PLL can provide the locked local signals for the GSM and WLAN bands as desired. Moreover, by integrating a switched inductor into the VCO circuit, the output oscillation frequency can generate the desired GSM and WLAN center frequency by turning the switch on and off. And by switching the capacitance array, the tuning range of the oscillator can be wider without the degradation of phase noise.
We also practice a divide-by-three circuit design in this thesis. In our Lab, we have proposed a RF synthesizer architecture for an UWB MB-OFDM system. Such RF synthesizer must use the base frequencies of 7128 MHz、3168 MHz、1584 MHz and 528 MHz. We plan to utilize a divide-by-three circuit to generate 528 MHz from 1584 MHz. For the above reason, a divide-by-three circuit is demanded. We utilize the principle of injection lock to implement the divide-by-three circuit
The contributions of this thesis are: The first, a PLL is proposed and taped out for the GSM/WLAN co-existence system. The second, we implement an injection locked divide-by-three circuit for UWB RF synthesizer use.

摘要.......................................................................................................... III
Abstract.....................................................................................................IV
LIST OF TABLES...................................................................................XI
LIST OF FIGURES................................................................................XII
Chapter1 Introduction .....................................1
1-1 Brief Introduction.....................................1
   1-1-1 The Brief Introduction of Global System for 
         Mobile Communications (GSM) Standard..............2
   1-1-2 The Brief Introduction of Wireless Local Area 
         Network(WLAN) Standard............................4
1-2 Motivation.............................................6
1-3 Thesis Organization....................................8
Chapter 2 The Principle of the PLL.........................9
2-1 Introduction...........................................9
2-2 Operation and Basic Structure of PLL .................10
2-3 Linearity Model of PLL................................11
   2-3-1 Transform Function...............................11
   2-3-2 Stability Issues.................................13
   2-3-3 Steady State Error of PLL........................15
   2-3-4 Transient Responses..............................16
2-4 Principle of Phase/Frequency Detector and Charge Pump.17
   2-4-1 Operation and Structure of PFD...................17
   2-4-2 Operation and Structure of Charge Pump...........19
   2-4-3 Nonlinear Effect.................................20
2-5 LPF...................................................23
2-6 VCO...................................................24
2-7 Divider...............................................25
2-8 Phase noise...........................................27
   2-8-1 Phase Noise in PLL Loop..........................29
Chapter 3 Design of PLL...................................33
3-1 Phase and Frequency Detector..........................33
3-2 Charge Pump...........................................35
3-3 Low Pass Filter.......................................37
3-4 Switched Inductor and VCO ............................38
   3-4-1 Switched Inductor................................39
   3-4-2 VCO..............................................40
3-5 Divider ..............................................42
   3-5-1 Two-modulus Prescaler............................43
   3-5-2 TSPC.............................................44
   3-5-3 Programmable Counter.............................45
3-6 Layout and Photo of PLL...............................47
Chapter 4 Simulation Results of PLL.......................49
4-1 Introduction..........................................49
4-2 Sub-circuits of Phase lock loop ......................49
   4-2-1 Phase/Frequency Detector ........................49
   4-2-2 Charge pump .....................................53
   4-2-3 VCO..............................................55
         4-2-3-1 Tuning Range of VCO......................55
         4-2-3-2 Phase Noise of VCO.......................57
         4-2-3-3 Summaries of Frequency Range and Phase 
                 Noise....................................58
         4-2-3-4 Pre-amplifier............................59
   4-2-4 Divider..........................................59
         4-2-4-1 Prescaler................................59
         4-2-4-2 Programmable Counter.....................61
         4-2-4-3 Module Control Logic.....................62
         4-2-4-4 Divider..................................63
4-3 PLL System Simulation.................................64
4-4 Performance of PLL....................................69
Chapter 5 Measurement Results of PLL......................71
5-1 Measurement Considerations............................71
5-2 Power Spectrum........................................72
5-3 Phase Noise of PLL....................................75
5-4 Phase Noise of VCO....................................77
5-5 Discussion............................................79
5-6 Performance of PLL....................................82
Chapter 6 A High-Speed Analog Divide-by-Three Circuit.....83
6-1 Brief Introduction of UWB.............................83
6-2 Motivation............................................84
6-3 Principle of Injection Locked Divider.................86
6-4 Divide-by-Three Structure.............................87
6-5 Simulation Result of Divide-by-Three..................88
   6-5-1 Simulation.......................................88
   6-5-2 Simulation Result................................89
6-6 Measurement Results...................................90
   6-6-1 Measurement Considerations.......................90
   6-6-2 Introduction of Hybrid-Ring Coupler..............92
        6-6-2-1 Simulation of Hybrid-Ring Coupler.........92
        6-6-2-2 Simulation Results of Hybrid-Ring Coupler.93
        6-6-2-3 Measurement Results of Hybrid-Ring 
                Coupler...................................97
   6-6-3 Measurement Results of Injection Lock Divider ..100
        6-6-3-1 Power Spectrum...........................100
        6-6-3-2 Phase Noise..............................101
        6-6-3-3 Locking Range............................105
        6-6-3-4 Performance of Injection-Lock Divider....105
6-7 Layout and Photo of Divide-by-Three..................106
Chapter 7 Conclusions and Future Work....................107
7-1 Conclusions..........................................107
7-2 Future Work..........................................108
Reference............................................... 111
                                    

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校內：2008-08-22公開
校外：2010-08-22公開

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