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研究生：	張世欣 Chang, Shih-Hsin
論文名稱：	使用跳頻鎖定技術應用於超寬頻之快速跳頻頻率合成器 A Fast-Hopping Frequency Synthesizer using Jumping-Lock Technique for UWB Applications
指導教授：	黃尊禧 Huang, Tzuen-Hsi
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	74
中文關鍵詞：	頻率合成器、跳頻鎖定、鎖相迴路
外文關鍵詞：	phase-locked loop, Frequency synthesizers, jumping lock
相關次數：	點閱：94 下載：4
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本論文提出一構想主要利用基本鎖相迴路加上切換訊號來，在頻率改變時達到快速切換和快速鎖定。傳統式的鎖相迴路鎖定時間通常需要幾微秒以上，使用跳頻鎖定架構代替傳統式架構，切換時間加上鎖定時間能被減少到小於10奈秒。快速鎖定能應用於3~10 GHz MB- OFDM UWB 頻率合成器來減少電路複雜度。此實驗基本架構為2.4 GHz整數型鎖相迴路利用0.18-μm CMOS製程來實作，實驗結果顯示當輸出頻率切換在2.2 GHz~2.4 GHz時，跳頻鎖定時間大約3.7奈秒 (約 0.6% 頻率誤差)而傳統鎖頻式頻率合成器大約為5.2微秒。

附錄為設計一應用於25 GHz四相位注入式除三電路。利用傳統式的電晶並聯體耦合四相位LC振盪器合技術來產生四相位，此除三電路實現於0.18-μm CMOS 製程，輸入為+4 dBm下其除頻範圍從25.16 ~ 25.71 GHz大約550 MHz，量測結果在輸出為8.4 GHz下二階及三階諧波抑制大約為34.12 dBc 和18.66 dBc，注入訊號為+4 dBm時相位雜訊再100 KHz時大約為-113 dBc/Hz，電源為1.8 V功率消耗大約為36 mW，相位誤差大約為2.8度，free-running相位雜訊在距離中心頻率100 KHz 大約為-70 dBc/Hz 。

This thesis proposes an idea for implementing a phase-locked-loop (PLL)-based switchable gigahertz signal generator with an extremely fast switching and settling time when the frequency switches. The settling time of traditional tracking lock PLL is usually up to microsecond. Using a jumping lock mechanism instead of the traditional tracking lock in a PLL, the total switching and settling time can be reduced to less than 10 ns. This fast-switching feature can be applied to the 3 to 10 GHz multi-band orthogonal frequency division multiplexing (MB- OFDM) ultra-wideband (UWB) frequency synthesizers to reduce the circuit complexity. The experimental verification is conducted by a prototype circuit based on a 2.4 GHz integer-N PLL fabricated in a 0.18-μm CMOS process. The measured switching and settling time (with 0.6% frequency error) is about 3.7 ns with the jumping lock, while about 5.2μs with the tracking lock, for the output frequency switching between 2.2 GHz and 2.4 GHz.

The design of a CMOS injection-locked divide-by-3 frequency divider operated at 25 GHz with quadrature outputs are shown in the appendix. The quadrature outputs are generated by a modified topology of a conventional parallel-transistor-coupled quadrature LC-oscillator. The prototype circuit is realized in a 0.18-m RF CMOS technology with a locking range of 550 MHz (from 25.16 to 25.71 GHz) with respect to +4 dBm input incident power. The measured second- and third-order harmonic suppressions are 34.12 dBc and 18.66 dBc, respectively, with respect to the divided output frequency of 8.4 GHz. The phase noise under lock is -113 dBc/Hz at 100 KHz offset with +4 dBm injection power. This prototype consumes 36 mW from 1.8 V supply. The maximum phase difference between the in- and quadrature-phase signals measured is about 2.8. The free-running phase noise is around -70 dBc/Hz at 100 kHz offset from the center frequency.

CONTENTS

Chapter1Introduction.....................................1
1-1 Background …………………………	……………..…..1
1-2 Motivation………………	………… ………….….……3
1-3Thesis Organization……………………  ……...………4
Chapter2 The principle of the PLL....................5
2-1 Linearity model of PLL………… ……..………………5
 2-1-1 Transfer function……………………………… ……6
 2-1-2 Stability issues………………… ……………… …9
2-2 Jumping lock…………………… ……………………….14
2-3 Application to UWB frequency synthesizer… …….21
Chapter 3 Circuit implementation of PLL          …………22
3-1 Theorem ………………………………………  …………22
3-2 Design flow……………………… ………………………23
 3-2-1 Parameter calculation ………… ………… …   24
 3-2-2 Circuit structure………………… ………… ……25
3-3 Phase frequency detector (PFD)………………………27
3-4 Charge-pump and low pass filter (LPF)…… ………31
3-5 Voltage control oscillator (VCO)……    …………33
3-6 Divider…………………………………………… ………35
 3-6-1 Prescaler…………   …………………………  … 35
 3-6-2 Programmable counter……………………………… 37 
3-7 Layout and photo of PLL…………………………   …39

Chapter 4 Measurement results of PLL…	……………40
4-1 Measurement results……………………………     …40
Chapter 5 Conclusions and future work             …48
5-1 Conclusions………………………	…………     …48
5-2 Future work…  ……………       ……………………49
References…………………………      	 …………………50
Appendix A 
K-Band Injection-Locked Divide-by-Three Frequency Divider with Quadrature Outputs     	… ………………53
A.1 Introduction…………………………………… ………53
A.2 Circuit design………………………… ………………54
A.3 Experimental results………………………………….58
A.4 Conclusion and future work………………… ………62
References………………………………… …………………63
Appendix B
PLL simulation by simulink and experiment results arrangement by C language…………      ………………65
B.1 Introduction…………………………………………….65
B.2 Building PLL model………………………………… ..65
 B.2-1 Building PFD……………………	…………… …..65
 B.2-2 Building charge pump and low pass filter…..66
 B.2-3 Building VCO………………………………………..68
 B.2-4 Building divider…………………………………..68
 B.2-5 Building subsystem and parameters………  ….69
B.3 Simulation of PLL………………	………………….70
B.4 Simulation results of PLL………………………...70
B.5 Measurement data segment…………………………...71
 B.5-1 Program………………….…………………………….72
B.5-2 Locking time plot……………………	………74
                                    

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校內：2012-07-28公開
校外：2015-07-28公開

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