目前有越來越多的消費性產品能支援多種視訊壓縮格式，如何去設計出能支援多種標準的硬體是很重要的。在本論文中，為了實現低成本的硬體設計，我們提出了一個應用於多個標準的整合性反轉換架構，此架構能有效地被使用於H.264/AVC，VC-1以及AVS解碼器中。我們利用轉換矩陣本身的對稱性質，就可以有效率地簡化原本繁複的矩陣乘法運算，藉由此結果，在硬體設計上並不需要使用到乘法器即可完成所需的反轉換運算。在此架構中，只需要使用移位器以及加/減法器，即可快速地完成H.264/AVC，VC-1以及AVS所定義的一維反轉換運算。由模擬結果得知，我們所提出的架構所需的邏輯閘數目為8,983，此邏輯閘數量遠少於沒有使用硬體共享的架構。當與個別標準的硬體設計相比時，此架構能減少約54.9%的邏輯閘數量。

Hardware designs that can support multiple standards are required for versatile media players. This thesis proposes a unified inverse transform architecture that can be efficiently used in MPEG and ITU-T H.264/AVC, Microsoft VC-1, and Chinese AVS decoders. For H.264/AVC 8-point and 4-point inverse transforms, the computational complexity in the proposed architecture is similar to that defined in the H.264/AVC standard. By using the symmetry property of the transform matrices, the matrix product operations of the inverse transforms in VC-1 and AVS are efficiently decomposed to only use shifters, adders, and subtractors. All the computations are verified and designed using a hardware unit to achieve a low-cost hardware kernel. The proposed multiple-transform architecture contains fast 1-D transforms and rounding operations for the computation of H.264/AVC, VC-1, and AVS 8-point and 4-point inverse transforms. Simulation results show that the total number of gates for the proposed architecture is 8,983, which is much less than that required for architectures without hardware sharing. Compared to individual designs, the proposed architecture reduces the number of logic gates by up to 54.9%.

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