在這篇論文當中，我們將介紹設計一個雙模式的渦輪碼/迴旋碼系統的過程與電路實現結果。很明顯的在我們介紹的系統包含了渦輪碼的編解碼器與回旋碼編解碼器兩大主要部分。分別用來對渦輪碼與迴旋碼做編碼以及解碼的動作。
隨著現代化的數位系統與行動通訊系統中資料傳輸的機會慢慢增加，資料在傳輸過程保持正確變得越來越重要。因此錯誤控制編碼也就扮演著越來越吃重的角色。我們便是希望能夠設計出有這種能力的電路系統。而渦輪碼也因為他能改正迪續性的錯誤而成為目前最受觀迎的改錯碼之一。除此之外，渦輪碼與迴旋碼都在第三代的行動通訊系統中被採用當成標準。這就是為何我們希望能夠設計出這個電路系統。
在此論文中我們不僅會對於這兩種改錯碼的理論部分做一些介紹還會將整個設計的過程與實現的結果呈現出來。而在設計的過程中，我們會先使用C++對系統做軟體的模擬，隨後則是使用Verilog 硬體描述語言來對系統做設計，待電路設計完成後則是利用Xilinx Foundation第四版的軟體來對電路做合成與模擬的動作以便驗証所設計出來的電路是否可正確操作。

This Paper present a design process and result of a dual mode turbo/ convolutional codec IP. It is obvious that the IP we designed have two major function. One is the encoding and decoding of the turbo code and the other is the encoding and decoding of the convolutional code.
As the increasing opportunities of the data transfer of the modern digital or mobile communication, the reliability of the data transfer has become more and more important. Therefore, the FEC have played an very important role nowadays. The motivation of this paper is to design an IP which could provide the ability of error control. The turbo code is one of the most popular of the error correcting code at present due to its correct ability of the burst errors. Besides, the convolutional and turbo code are adapted in the 3G mobile communication standard.This is why we intend to design a dual mode IP with the convolutional and turbo codec.
In this paper we introduce not only the conception and theorem but also the implementation of the IP. In the design process, we achieve software simulation of both two codec with C++ and then we implement it by Verilog. After the coding process with the verilog, we take use of the Xilinx foundation 4.1 to help us simulate the hardware we have designed.

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