本論文提出相關電壓位移平均(ACLS)及參考電壓交換(RS)技術以同時降低高解析導管式類比數位轉換器(ADC)之運算放大器有限增益誤差及電容不匹配誤差。ACLS技術使第二放大相位產生與第一放大相位極性相反之誤差，並進而平均兩個放大相位電壓以消除ADC之運算放大器有限增益誤差，同時也能降低運算放大器之熱雜訊。此外，本論文亦提出RS技術降低電容隨機不匹配誤差，並結合簡化的電容佈局擺放方式降低電容梯度不匹配誤差。將所提之技術以90 nm CMOS製程實現於16位元環形放大器基底之導管式ADC，此晶片尺寸為0.368 mm2。量測結果顯示，此ADC操作於24 MS/s以及輸入訊號為10 MHz時，SNDR可達到74 dB且其功耗為5.1 mW，而其對應之Walden及Schreier效能指標(FOMW及FOMS)分別為50.1 fJ/conversion-step and 168 dB。

本論文亦提出電容排序平均(SCA)技術用於差動輸入之ADC，分別排序兩側之電容陣列，獲得其電容相對大小後，即可使兩側之電容不匹配誤差互相補償。為了驗證電容排序平均技術，本論文實現一個雙模16位元導管式ADC，兩個模式為電容排序平均(SCA)及兩相位平均(TPA)，分別採用SCA及RS技術降低電容不匹配誤差，且兩個模式皆採用ACLS技術解決OPAMP有限增益誤差。並以90 nm CMOS製程實現此16位元導管式ADC，此晶片尺寸為0.506 mm2。量測結果顯示，此雙模ADC分別操作於40/30 MS/s以及輸入訊號為20/15 MHz時，SNDR可達到71.2/74.5 dB且其功耗為5.5/5.2 mW，而其對應之效能指標FOMW及FOMS分別為46.3/40.0 fJ/conversion-step and 166.8/169.1 dB。此外，此雙模ADC操作在TPA模式時，與其他頂尖文獻具取樣速度>20 MS/s且SNDR>72 dB之ADC相比有最佳效能指標。

最後，為了進一步降低功耗，本論文將ACLS及RS技術實現於導管式逐漸趨近式(Pipelined SAR) ADC。此外，本論文提出一個技術用以提高此Pipelined SAR ADC之操作速度。並以28 nm CMOS製程實現上述技術於14位元130MS/s Pipelined SAR ADC，此晶片尺寸為0.025 mm2。佈局後之模擬結果顯示，當輸入訊號為Nyquist頻率時，SNDR可達到72 dB且其功耗為2.2 mW，而其對應之效能指標FOMW及FOMS分別為5.2 fJ/conversion-step and 176.7 dB。此外，此ADC與其他頂尖文獻具取樣速度>100 MS/s且SNDR>62 dB之ADC相比有最佳效能指標。

This dissertation proposes averaging correlated level shifting (ACLS) and reference swapping (RS) techniques for simultaneously reducing errors from the finite opamp gain and capacitor mismatch in a high-resolution pipelined analog-to-digital converter (ADC). The ACLS technique reduces the sensitivity of ADC accuracy to the opamp gain by averaging the finite opamp gain errors in two amplifying phases, where the error in the second amplifying phase is designed to have the opposite polarity to the one in the first amplifying phase. Meanwhile, ACLS also decreases the opamp’s thermal noise. In addition, the RS utilizes the averaging operation to reduce capacitor random mismatch error and combines a simple capacitor layout arrangement to decrease capacitor gradient mismatch error. Using the ACLS and RS techniques, a 16-bit ring amplifier-based pipelined ADC without calibration is realized in 90 nm CMOS technology, which has an active area of 0.368 mm2. Measurement results shows that the ADC achieves a 74.3 dB SNDR and at 24 MS/s for a 10 MHz sine-wave input, and consumes 5.1 mW, yielding Walden and Schreier Figure-of-Merits (FoMW and FoMS) of 50.1 fJ/conversion-step and 168 dB, respectively.

This dissertation also proposes sorted-capacitor averaging (SCA) technique that executes a capacitor-sorting procedure before ADC operation. After acquiring the relative sizes of the capacitors by the sorting procedure, the top- and bottom-side capacitors of a differential pipelined ADC, can compensate each other’s mismatch errors. In addition, the two capacitor mismatch error reduction techniques, SCA and RS, are combined with the finite opamp gain error reduction technique, ACLS, in SCA and two-phase averaging (TPA) modes of the proposed 16-bit ADC, respectively. The 16-bit ADC is realized in 90 nm CMOS technology, which has an active area of 0.506 mm2. For 20 MHz and 15 MHz input sampling at 40/30 MS/s, the ADC operating in SCA/TPA modes achieves 71.2/74.5 dB measured SNDR with a power consumption of 5.5/5.2 mW, yielding FoMW and FoMS of 46.3/40.0 fJ/conversion-step and 166.8/169.1 dB, respectively. Furthermore, the proposed ADC in TPA mode achieves the best FoMW and FoMS among prior state-of-the-art Nyquist ADCs with sampling rates larger than 20 MS/s and SNDR greater than 72 dB.

Finally, to further reduce the power consumption, the ACLS and RS are applied in a pipelined SAR ADC. In addition, this dissertation proposes a speed enhancement technique for the pipelined SAR ADC. A 14-bit 130 MS/s pipelined SAR ADC is realized in 28 nm CMOS technology, which has an active area of 0.025 mm2. Post-simulation results shows that the ADC achieves a 72 dB SNDR for a Nyquist input, and consumes 2.2 mW, yielding FoMW and FoMS of 5.2 fJ/conversion-step and 176.7 dB, respectively. Furthermore, the proposed ADC achieves the best FoMW and FoMS among prior state-of-the-art Nyquist ADCs with sampling rates larger than 100 MS/s and SNDR greater than 62 dB.

[1] A. N. Karanicolas, H.-S. Lee, and K. L. Bacrania, “A 15-b 1-Msample/s digitally self-calibrated pipeline ADC,” IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1207–1215, Dec. 1993.
[2] A. Verma and B. Razavi, “A 10-bit 500-MS/s 55-mW CMOS ADC,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3039–3050, Nov. 2009.
[3] H.-C. Liu, Z.-M. Lee, and J.-T. Wu, “A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration,” IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1047–1056, May 2005.
[4] H. Van de Vel, B. A. J. Buter, H. van der Ploeg, M. Vertregt, G. J. G. M. Geelen, and E. J. F. Paulus, “A 1.2-V 250-mW 14-b 100-MS/s digitally calibrated pipeline ADC in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1047–1056, Apr. 2009.
[5] A. Panigada and I. Galton, “A 130 mW 100 MS/s pipelined ADC with 69 dB SNDR enabled by digital harmonic distortion correction,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3314–3328, Dec. 2009.
[6] R. Sehgal, F. van der Goes, and K. Bult, “A 12 b 53 mW 195 MS/s pipeline ADC with 82 dB SFDR using split-ADC calibration,” IEEE J. Solid-State Circuits, vol. 50, no. 7, pp. 1592–1603, Jul. 2015.
[7] B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U.-K. Moon, “Ring amplifiers for switched capacitor circuits,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2928–2942, Dec. 2012.
[8] B. Hershberg and U.-K. Moon, “A 75.9dB-SNDR 2.96mW 29fJ/conv-step ringamp-only pipelined ADC,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2013, pp. C94–C95.
[9] Y. Lim and M. P. Flynn, “A 1 mW 71.5 dB SNDR 50 MS/s 13 bit fully differential ring amplifier based SAR-assisted pipeline ADC,” IEEE J. Solid-State Circuits, vol. 50, no. 12, pp. 2901–2911, Dec. 2015.
[10] Y. Lim and M. P. Flynn, "A calibration-free 2.3 mW 73.2 dB SNDR 15b 100 MS/s four-stage fully differential ring amplifier based SAR-assisted pipeline ADC," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2017, pp. C98–C99.
[11] B. R. Gregoire and U.-K. Moon, “An over-60 dB true rail-to-rail performance using correlated level shifting and an opamp with only 30 dB loop gain,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2620–2630, Dec. 2008.
[12] B. Hershberg, S. Weaver, and U.-K. Moon, “Design of a split-CLS pipelined ADC with full signal swing using an accurate but fractional signal swing opamp,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2623–2633, Dec. 2010.
[13] B. Hershberg, T. Musah, S. Weaver, and U.-K. Moon, “The effect of correlated level shifting on noise performance in switched capacitor circuits,” in Proc. IEEE Int. Symp. Circuits and Syst. (ISCAS), May 2012, pp. 942–945.
[14] J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, “A 12-bit intrinsic accuracy high-speed CMOS DAC,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1959–1969, Dec. 1998.
[15] G. A. M. Van der Plas, J. Vandenbussche, W. Sansen, M. S. J. Steyaert, and G. G. E. Gielen, “A 14-bit intrinsic accuracy Q2 random walk CMOS DAC,” IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1708–1718, Dec. 1999.
[16] P. C. Yu and H.-S. Lee, “A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC,” IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1854–1861, Dec. 1996.
[17] J. Yang and H.-S. Lee, “A CMOS 12-bit 4 MHz pipelined A/D converter with commutative feedback capacitor,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), May 1996, pp. 427–430.
[18] Y. Chiu, P. R. Gray, and B. Nikolic, “A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2139–2151, Dec. 2004.
[19] C.-H. Kuo and T.-H. Kuo, “Capacitor-swapping cyclic A/D conversion technique with reduced mismatch sensitivity,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 12, pp. 1219–1223, Dec. 2008.
[20] W. Yang, D. Kelly, I. Mehr, M. T. Sayuk, and L. Singer, “A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1931–1936, Dec. 2001.
[21] S. Devarajan, L.Singer, D. Kelly, S. Decker, A.Kamath, and P.Wilkins, “A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS pipeline ADC,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3305–3313, Dec. 2009.
[22] S. Ray and B.-S. Song, “A 13-b linear, 40-MS/s pipelined ADC with self-configured capacitor matching,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 463–474, Mar. 2007.
[23] B. Gregoire and U.-K. Moon, “Reducing the effects of component mismatch by using relative size information,” Proc. IEEE Int. Symp. Circuits Syst., May 2008, pp. 512–515.
[24] B. Verbruggen, et al., “A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2014, pp. 1–2.
[25] Y. Zhou et al., “A 12 bit 160 MS/s two-step SAR ADC with background bitweight calibration using a time-domain proximity detector,” IEEE J. Solid-State Circuits, vol. 50, no. 4, pp. 920–931, Apr. 2015.
[26] V. Hariprasath, J. Guerber, S.-H. Lee, and U.-K. Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” Electron. Lett., vol. 46, no. 9, pp. 620–621, Apr. 2010.
[27] H.-Y. Tai, Y.-S. Hu, H.-W. Chen, and H.-S. Chen, “A 0.85 fJ/conversion-step 10b 200 kS/s subranging SAR ADC in 40 nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2014, pp. 196–197.
[28] T.-C. Hung and T.-H. Kuo, “A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting technique,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2016, pp. 161–164.
[29] R. Schreier, J. Silva, J. Steensgaard and G. C. Temes, “Design-oriented estimation of thermal noise in switched-capacitor circuits,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 11, pp. 2358–2368, Nov. 2005.
[30] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization,” Proc. IEEE, vol. 84, no. 11, pp. 1584–1614, Nov. 1996.
[31] W.-T. Lin, H.-Y. Huang, and T.-H. Kuo, “A 12-bit 40 nm DAC achieving SFDR > 70 dB at 1.6 GS/s and IMD < –61 dB at 2.8 GS/s with DEMDRZ technique,” IEEE J. Solid-State Circuits, vol. 49, no. 3, pp. 708–717, Mar. 2014.
[32] J. Brunsilius, E. Siragusa, S. Kosic, F. Murden, E. Yetis, B. Luu, J. Bray, P. Brown, and A. Barlow, “A 16b 80MS/s 100mW 77.6dB SNR CMOS pipeline ADC,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp. 186–188.
[33] M. J. Kramer, E. Janssen, K. Doris and B. Murmann, "A 14 b 35 MS/s SAR ADC achieving 75 dB SNDR and 99 dB SFDR with loop-embedded input buffer in 40 nm CMOS," IEEE J. Solid-State Circuits, vol. 50, no. 12, pp. 2891–2900, Dec. 2015.
[34] H. Xu, Y. Cai, L. Du, Y. Zhou, B. Xu, D. Gong, J. Ye, and Y. Chiu, “A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2017, pp. 476–477.
[35] J. Shen et al., "A 16-bit 16-MS/s SAR ADC with on-chip calibration in 55-nm CMOS," IEEE J. Solid-State Circuits, vol. 53, no. 4, pp. 1149–1160, Apr. 2018.
[36] S. Leuenberger, J. Muhlestein, H. Sun, P. Venkatachala, and U.-K. Moon, “A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using dynamic deadzone ring amplifier,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), May 2017, pp. 1–4
[37] D.-Y Chang et al., “A 21mW 15b 48MS/s Zero-Crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR,” ISSCC Dig. Tech. Papers, pp. 204–205, Feb. 2014.
[38] H. Venkatram et al., “A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2014, pp. 46–47.
[39] H.-Y Lee, B. Lee, and U-K. Moon, " A 31.3fJ/conversion-step 70.4dB SNDR 30MS/s 1.2V two-step pipelined ADC in 0.13μm CMOS," in ISSCC Dig. Tech. Papers, Feb. 2012, pp. 474–475.
[40] B. Murmann, “ADC Performance Survey 1997-2018,” [Online]. Available: http://web.stanford.edu/~murmann/adcsurvey.html
[41] K. Yoshioka et al., “A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique,” in ISSCC Dig. Tech. Papers, Feb. 2017, pp. 478–479.
[42] S.-W. Chen and R. W. Brodersen, “A 6b 600 MS/s 5.3 mW asynchronous ADC in 0.13 m CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 2350–2351.
[43] E. Martens, et al., “A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET with Capacitive Reference,” in IEEE J. Solid-State Circuits, vol. 53, no. 4, pp. 1161–1171, Apr. 2018.
[44] J. P. Mathew, et al., “A 12-Bit 200-MS/s 3.4-mW CMOS ADC with 0.85-V Supply,” in IEEE Symp. VLSI Circuit Dig. Tech. Papers, Jun. 2015, pp. C66–C67.
[45] H. Huang, et al., “A 12b 330MS/s Pipelined-SAR ADC with PVT-stabilized Dynamic Amplifier Achieving <1dB SNDR Variation,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2017, pp. 472–473.