簡易檢索 / 詳目顯示

回結果列表
研究生： 鄭宇栢
Cheng, Yu-Po
論文名稱： 一個具簡潔控制迴路之8Gb/s半速率數位時脈與資料回復電路
An 8 Gb/s Half-rate Digital-based Clock and Data Recovery Circuit With Compact Control Loop
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2015
畢業學年度： 104
語文別： 英文
論文頁數： 68
中文關鍵詞： 鎖相迴路 、時脈與資料回復電路 、數位時脈與資料回復電路
外文關鍵詞： PLL, CDR, digital CDR
相關次數： 點閱：100  下載：1 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 本論文提出了在數位時脈與資料回復電路中簡化操作迴路以及將階梯式控制方法數位化兩個技巧來提升整體效能。藉由使用數位加法器整合頻率控制迴路與積分迴路，可以移除部分分支電路，減少整體電路的面積和功耗。再者，將階梯式控制方法數位化有效讓系統在不同環境下擁有更穩定的頻寬。此數位化時脈與資料回復電路晶片以互補式金屬氧化物半導體 90-nm製程進行設計與驗證。以7Gb/s PRBS7的輸入資料測試時，所得到的量測同步時脈與資料訊號之方均根抖動值與和時脈周期的比值分別是9.25ps[3.2%]和13.66ps[0.048UI]。而峰對峰值則分別是22.5% [64.38ps]和0.23UI [65.63ps]。此核心電路面積和功耗分別約是0.054 mm2和1.623 mW/Gb/s。

    This thesis presents a compact control loop and a digitalized stepwise control method to improve area and power efficiency performance for digital-based CDRs. By combining the frequency control loop and integral path with a digital adder, some tributary circuits are removed to save total area and power. Meanwhile, the stepwise control technique proposed in [9] for constant system bandwidth is digitalized to enhance the system robustness. The digital-based CDR is designed and fabricated in 90-nm GUTM CMOS process. The measured root mean square (rms) jitter ratio of the synchronous clock and recovered data is 3.2% [9.25ps] and 0.048UI [13.66ps] and the peak to peak jitter is 22.5% [64.38ps] and 0.23UI [65.63ps] while the input data pattern is 7Gb/s PRBS7. The core area of the test chip is 0.054 mm2 and its power efficiency is 1.623 mW/Gb/s.
    Keyword: PLL, CDR, digital-based CDR.

    Table of Contents List of Table 1 List of Figure 1 Chapter 1 Introduction 5 1-1 MOTIVATION 5 1-2 THESIS ORGANIZATION 8 Chapter 2 PLL, CDR, Digital-based CDR 9 2-1 FIBER-OPTICS COMMUNICATION 9 2-2 PHASE-LOCKED LOOP (PLL) 10 2-2-1 Introduction to PLL 10 2-2-2 Qualitative of PLL 11 2-3 CLOCK AND DATA RECOVERY (CDR) 16 2-3-1 Introduction to CDR 16 2-3-2 Reference-less CDR Circuit and Frequency Detector 17 2-3-3 Phase detector and coupled JTRAN and JGEN in Clock and Data Recovery Circuit [8] [13] 20 2-4 DIGITAL-BASED CLOCK AND DATA RECOVERY 25 2-4-1 Architecture of Digital-base CDR 25 2-4-2 Design Consideration [10] [11] [12] 29 2-5 PERFORMANCE METRIC OF CLOCK AND DATA RECOVERY 31 Chapter 3 The proposed Digital-based CDR 34 3-1 SPECIFICATION 34 3-2 THE PROPOSED TECHNIQUE 35 3-2-1 Compact control loop 36 3-2-2 Digitalization of Stepwise Control 38 3-2-3 Architecture and System parameter design 39 3-3 CIRCUIT DESCRIPTION 42 3-3-1 DQFD [2] 42 3-3-2 Decimator 47 3-3-3 Delta Sigma Modulator and DAC 48 3-3-4 CCO and PI 50 3-3-5 Layout and Floorplan 52 Chapter 4 Simulation and Measurement Results 55 4-1 SIMULATION RESULTS 55 4-1-1 System Level Simulation 55 4-1-2 Circuit Level Simulation 56 4-2 MEASUREMENT RESULTS 61 4-3 COMPARISON TABLE 64 Chapter 5 Conclusions and Future Work 65 5-1 CONCLUSIONS 65 5-2 FUTURE WORK 65 Bibliography 67

    [1] V. Kratyuk, P. K. Hanumolu, U. K. Moon, and K. Mayaram, “Frequency Detector for Fast Frequency Lock Digital PLLs,” Electronics letters, vol. 43, pp. 13-14, Jan. 2007.
    [2] R.J. Yang, S.P. Chen, and S.I. Liu, “A 3.125-Gbs Clock and Data Recovery Circuit for the 10-Gbase-LX4 Ethernet,” IEEE J. Solid-State Circuits,” vol. 39, pp. 1356-1360, Aug. 2004.
    [3] D. Dalton, K. Chai, M. Ferriss, D. Hitchox, P. Murray, S. Selvanayagam, P. Shepherd, and L. Devito, “A 12.5 Mb/s to 2.7 Gb/s Continuous-Rate CDR with Automatic Frequency Acquisition and Data-Rate Readback,” IEEE J. Solid-State Circuits, vol. 40, pp. 2713-2725, Dec. 2005.
    [4] C. L. Hsieh and S. I. Liu, “A 1–16-Gb/s Wide-Range Clock/Data Recovery Circuit With a Bidirectional Frequency Detector,” IEEE Transactions On Circuits And Systems—II: Express Briefs, vol. 58, pp. 487-491, Aug. 2011.
    [5] R. Inti, W. Yin, A. Elshazly, N. Sasidhar, and P. K. Hanumolu, “A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance,” IEEE J. Solid-State Circuits, vol. 46, pp. 3150-3162, Dec. 2011.
    [6] B. J. Lee, M. S. Hwang, S. H. Lee, and D. K. Jeong, “A 2.5–10-Gb/s CMOS Transceiver With Alternating Edge-Sampling Phase Detection for Loop Characteristic Stabilization,” IEEE J. Solid-State Circuits, vol. 38, pp. 1821-1829, Nov. 2003.
    [7] J. Lee and K. C. Wu, “A 20Gb/s Full-rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition,” IEEE J. Solid-State Circuits, vol. 44, pp. 3590-3602, Dec. 2009.
    [8] W. Yin, R. Inti, A. Elshazly, M. Talegaonkar, B. Young and P. K. Hanumolu, “A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamic and Offset-Free Data Recovery,” IEEE J. Solid-State Circuits, vol. 46, pp. 3163-3173, Dec. 2011.
    [9] Y.-L. Lee, S.-J. Chang, R.-S. Chu, Y.-Z. Lin, Y.-C. Chen, J. R Goh, and C.-M. Huang, “A 5 Gb/s 1/4-rate Clock and Data Recovery Circuit Using Dynamic Stepwise Bang-bang Phase Detector,” IEEE Asian Solid-State Circuits Conference, 2012, pp. 141-144.
    [10] P. K. Hanumolu, M. G. Kim, G. Y. Wei1, and U. K. Moon, “A 1.6Gbps Digital Clock and Data Recovery Circuit,” IEEE Custom Integrated Circuits Conference, 2006, pp. 603-606.
    [11] G. Shu, S. Saxena, W. S. Choi, M. Talegaonkar, R. Inti, A. Elshazly, B. Young, and P.K. Hanumolu, “A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop,” IEEE J. Solid-State Circuits, vol. 49, pp. 1036-1047, Apr. 2014.
    [12] V. Kratyuk, P. K. Hanumolu, U. K. Moon, and K. Mayaram, “A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy,” IEEE Transactions On Circuits And Systems—II: Express Briefs, vol. 54, pp. 247-251, Mar. 2007.
    [13] M. Talegaonkar, R. Inti, and P. K. Hanumolu, “Digital Clock and Data Recovery Circuit Design: Challenges and Tradeoffs,” IEEE Custom Integrated Circuits Conference, 2011, pp. 1-8.
    [14] G. Shu, W.-S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. K. Hanumolu, “A 4-to-10.5Gb/s 2.2mW/Gb/s Continuous-Rate Digital CDR with Automatic Frequency Acquisition in 65nm CMOS,” IEEE International Solid-State Circuits Conference, 2014, pp. 150-151.
    [15] 劉深淵、楊清淵，”鎖相迴路”，滄海書局，2006。
    [16] B.-J. Lee, M.-S. Hwang, S.-H. Lee, and D.-K. Jeong, “A 2.5–10-Gb/s CMOS Transceiver With Alternating Edge-Sampling Phase Detection for Loop Characteristic Stabilization,” IEEE J. Solid-State Circuits, vol. 38, pp. 1821-1829, Nov. 2003
    [17] T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly, and P. K. Hanumolu, ”A 7Gb/s Rapid On/Off Embedded-Clock Serial-Link Transceiver with 20ns Power-On Time, 740uW Off-State Power for Energy-Proportional Links in 65nm CMOS,” IEEE International Solid- State Circuits Conference, 2015, pp. 1-3.
    [18] J. L. Sonntag and J. Stonick, “A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links,” IEEE J. Solid-State Circuits, vol. 41, pp. 1867-1875, Aug. 2006.
    [19] S.-K. Lee, Y.-S. Kim, H. Ha, S. Y, H.-J. P, J.-Y. S, “A 650 Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate,” IEEE International Solid- State Circuits Conference, 2009, pp. 184-185.
    [20] D. H. Oh, D.-S. Kim, S. Kim, D.-K. Jeong, W. Kim, “A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO,” IEEE International Solid- State Circuits Conference, 2007, pp. 222-598.

    無法下載圖示 校內：2020-11-26公開
    校外：不公開
    電子論文尚未授權公開，紙本請查館藏目錄
    QR CODE