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研究生：	黃偉禎 Huang, Wei-Chen
論文名稱：	利用共扼匹配之植入式生醫遙測系統雙頻低雜訊放大器及混波器 Dual band LNA/Mixer using conjugate matching for implantable biotelemetry
指導教授：	羅錦興 Luo, Ching-Hsing
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	英文
論文頁數：	74
中文關鍵詞：	生醫、混波器、低雜訊放大器、共扼匹配、雙頻
外文關鍵詞：	Conjugate matching, Biotelemetry, Mixer, LNA, Dual band
相關次數：	點閱：82 下載：2
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在這篇論文研究中，主要討論雙頻帶 2.4GHz與 5.2GHz的低雜訊放大器與混頻器，運用在植入式生物晶片上；這個射頻接收前端電路，內容為低雜訊放大器的輸出端和混波器的輸入端，以共扼匹配的方式整合在單一晶片，並操作在雙頻 2.4GHz與 5.2GHz。
此射頻前端電路單一整合晶片中，在 2.4GHz，功率增益為 2.2dB，雜訊指數為 15.5dB，輸入 1dB功率壓縮點為 -14.4dBm，輸入三階截斷點為 -0.5dBm，及在 5.2GHz，功率增益為 5.6dB，雜訊指數為 10.8dB，輸入 1dB功率壓縮點為 -15.5dBm，輸入三階截斷點為 -6dBm，總功率消耗為 8.28mW。
為了達成單一晶片和系統單晶片的設計目標，此前端電路輸入端採用晶片元件做為匹配的設計，以便日後和其他電路整合。在2.4GHz與5.2GHz的S11大於 10dB。射頻接收器前端電路的工作頻段，可經由外部本地震盪器的頻率切換，達到輸出 400MHz的應用。
此晶片以台積電 CMOS 0.18-μm 的製程實現，並完成量測和模擬比較討論。

This Thesis presents a fully integrated 2.4/5.2-GHz dual-band low-noise amplifier (LNA) / mixer for implantable biotelemetry application. By using conjugation matching, this front-end receiver circuit integrates LNA output and mixer input for single chip at the 2.4GHz and 5.2GHz frequency band. The front-end circuit exhibits a 2.2dB gain, a 15.5dB noise figure, IP1dB of -14.4dBm, and IIP3 of -0.5dBm at the 2.4GHz frequency band. The front-end circuit exhibits a 5.6dB gain, a 10.8dB noise figure, IP1dB of -15.5dBm and IIP3 of -6dBm at the 5.2GHz frequency band. This circuit exhibits a power consumption of 8.28mW from a 1.8-V supply. To achieve single chip design target, this chip input was designed without any off-chip matching component. The circuit exhibits S11 of more than 10dB at the 2.4GHz and 5.2GHz frequency. The front-end circuit was designed for operation frequency. By switching local oscillator (LO) frequency, we can achieve an output application at the 400MHz frequency. The chip has fabricated in a TSMC 0.18-μm CMOS technology. Moreover, the measurement and comparison with simulation had been done.

Chapter 1 Introduction................................	1
1	Motivation...................................	1
2	Thesis Organization..........................	2

Chapter 2 RF Fundamentals.............................	3
1	Introduction.................................	3
2	Receiver Architecture........................	3
2.1	Superheterodyne Architecture.................	4
2.2	Direct Conversion (Zero-IF) Architecture.....	5
2.3	Low-IF Architecture..........................	6
2.4	Image-Reject Architecture....................	8
2.4.1	Hartley receiver.............................	8
2.4.2	Weaver receiver..............................	9
3	Basic RF Fundamentals........................	10
3.1	Sensitivity..................................	10
3.2	Noise Figure (NF)............................	10
3.3	Linearity	....................................	11
3.3.1	1-dB compression point.......................	12
3.3.2	Third-order Intermodulation Distortion.......	13
3.4	Quality Factor (Q-Factor)....................	14

Chapter 3 Dual Band Low Noise Amplifier...............	16
1	Introduction.................................	16
2	Basic Topologies of Low Noise Amplifier......	16
3	Noise Analysis...............................	17
3.1	Shot Noise...................................	18
3.2	Thermal Noise................................	18
3.3	Flicker Noise................................	19
3.4	Standard MOS Noise Model.....................	19
3.5	Noise Model and Input Impedance..............	21
4	Dual-Band LNA Architecture...................	25
5	Dual-Band LNA Design Approach................	26

Chapter 4 Dual Band Mixer.............................	27
1	Introduction.................................	27
2	Basic Topologies of Mixer....................	27
2.1	Single-Balanced Mixer........................	27
2.2	Double-Balanced Mixer........................	28
3	Fundamentals of Mixer........................	29
3.1	Conversion Gain..............................	29
3.2	Linearity....................................	30
3.3	Noise Figure.................................	32
3.4	Power consumption............................	33
3.5	Port-to-Port Isolation.......................	33
4	Dual-Band Mixer of This Work.................	34

Chapter 5 Conjugate Matching..........................	35
1	Return Loss..................................	35
2	Conjugate Matching...........................	35
3	Conjugate Matching for This Work.............	38

Chapter 6 Implementation of the 2.4 & 5.2 GHz Dual-Band LNA and Mixer.........................................	41
1	Implementation of Dual-Band LNA and Mixer....	41
2	Simulation Results...........................	42
2.1	Simulation Results...........................	42
2.2	Corner Check.................................	50
3	Layout of Dual-Band LNA and Mixer............	51
4	Post-Simulation..............................	52
5	On Board PCB Layout Consideration............	53
6	Measurement Consideration....................	54
7	Dual band LNA/Mixer Measurement..............	56
7.1	S-Parameter..................................	57
7.2	IP1dB and IIP3...............................	60
7.3	Gain and Noise Figure........................	62
7.4	Compare with Simulation Results..............	63
7.5	Problem Discussions..........................	63
7.5.1	Drift of frequency...........................	64
7.5.2	Compare with Simulation and Measurement Results	.............................................	67
7.5.3	Other factors and answers....................	67
8	Summary......................................	68

Chapter 7 Conclusion and Future Work..................	70
1	Conclusion...................................	70
2	Solutions of Inaccuracy......................	70
2.1	Process of Design............................	70
2.2	Process of Simulation........................	71
2.3	Process of Measurement.......................	71
3	Future Work..................................	71

REFERENCES............................................	72
                                    

[1]M. Zargari, M. Terrovitis, S.H.M. Jen, B.J. Kaczynski, L. MeeLan, M.P. Mack, S.S. Mehta, S. Mendis, K. Onodera, H. Samavati, W.W. Si, K. Singh, A. Tabatabaei, D. Weber, D.K. Su, B.A. Wooley, ”A Single- Chip Dual-Band Tri-Mode CMOS Transceiver for IEEE 802.11a/b/g WLAN,” IEEE J. Solid-State Circuits, Vol.39, pp.2239- 2249, Dec. 2004.

[2]M. Zannoth, T. Ruhlicke, B. U. Klepser,”A Highly Integrated Dual-Band Multimode Wireless LAN Transceiver,” IEEE J. Solid-State Circuits, Vol. 39, pp. 1191 - 1195, Jul. 2004.

[3]Adiseno; M. Ismail, H. Olsson, ”A Wide-Band RF Front-End for Multiband Multistandard High-Linearity Low-IF Wireless Receivers,” IEEE J. Solid-State Circuits, Vol.37,pp.1162-1168, Sep. 2002.

[4]Christina F. Jou, Kuo-Hua Cheng, Wei-Cheng Lien, Chun-Hsien Wu, and Chin-Hsien Yen, “Design of a Concurrent Dual-Band Receiver Front-End in 0.18um CMOS for WLANs IEEE 802.11a/b/g Applications,” IEEE Transaction on Microwave Theory and Techniques Mini-Special Issue on APMC 2004, New Delhi, India, Dec. 15-18, 2004.

[5]Zhenbiao Li, Richard Quintal, and Kenneth K. O, “A Dual-Band CMOS Front-End With Two Gain Modes for Wireless LAN Applications,” IEEE J. Solid-State Circuits, Vol. 39, No. 11, Nov. 2004.

[6]C.C. Hou, C.C. Chang, and C.K. Wang, “A Dual-band IEEE 802.11a/b/g Receiver Front-end Using Half-IF and Dual-Conversion,” IEEE Asia-Pacific Conference on Advanced System Integrated Circuits(AP-ASIC2004), Aug. 4-5. 2004.

[7]C.M. Hsu, C.M. Lee, T.C. Yo, C.H. Luo, “The Low Power MICS band biotelemetry architecture and its LNA design for implantanble applications,” IEEE Asian Solid-State Circuits Conference, Hangzhou, China, pp. 435-438, Nov. 2006.

[8]T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge, 1998.

[9]T. Cho, E. Dukatz, M. Mack, D. MacNally, M. Marringa, S. Mehta, C. Nilson, L. Plouvier, and S. Rabii, “A Single-Chip CMOS Direct-Conversion Transceiver for 900MHz Spread-Spectrum Digital Cordless Phones,” Digest of Technical Papers, ISSCC, pp. 228-229, Feb. 1999.

[10]P. J. Chang, A. Rofougaran, and A. A. Abidi, “A CMOS Channel-Select Filter for a Direct-Conversion Wireless Receiver,” Digest of Technical Papers, Symposium on VLSI Circuits, Honolulu, HI. pp. 62-63, Jun. 1996.

[11]T. Cho, G. Chien, F. Britanti, and P.R. Gray, “A Power-Optimized CMOS Baseband Channel Filter and ADC for Cordless Application,” Digest of Technical Papers, Symposium on VLSI Circuits, Honolulu, HI. Pp. 64-65, Jun. 1996.

[12]D. K. Weaver. “A Third Method of Generation and Detection of Single-Sideband Signal,” Proc. IRE, Vol. 44, pp. 1703-1705, Dec. 1956.

[13]M. Banu, H .Wang, M. Seidel, M. Tarsia, W. Fischer, J. Glas, A. Dec, and V. Boccuzzi, “A BiCMOS Double-Low-IF Receiver for GSM,” Digest of Technical Papers, IEEE Custom Integrated Circuits Conference, pp. 521-524, May 1997.

[14]R. Hartley, Modulation system, U.S. Patent 1666206, Aug. 1928.

[15]D. K. Weaver, Jr., “A third method of generation and detection of single-sideband signals,” Proc. IRE, pp. 1703-1705, Jun. 1956.

[16]B. Razavi, RF Microelectronics, Prentice Hall PTR, 1998.

[17]Derek K. Shaeffer, and Thomas H. Lee, “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier,” IEEE Jouranl of Solid-State Cirecuit, Vol. 32, No. 5, pp. 745, May 1997.

[18]Paul R. Gray, Paul J. Hurst, Stephen H. Lewis ,and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, Inc., Fourth Edition, 2001.

[19]A. ven der Ziel, Noise in solid State Devices and Circuit, New York: Wiley, 1986.

[20]H. Hashemi, A. Hajimiri, “Concurrent Multiband Low-Noise Amplifiers-Theory, Design, and Applicatons,” IEEE Tran. On Microwave Theory and Techniques, Vol. 50, No. 1, pp. 288-301, Jan. 2002.

[21]M. Ben Amor, A. Fakhfakh, H. Mnif, M. Loulou, “Dual Band CMOS LNA Design With Current Reuse Topology,” in DTIS 2006, pp. 57 - 61

[22]Pietro Andreani, and Henrik Sjöland, “Noise Optimization of an Inductively Degenerated CMOS Low Noise Amplifier,” IEEE Tran. On Circuits and Systems—II: Analog and Digital Signal Processing, Vol. 48, No. 9, Sep. 2001.

[23]Q. Huang, P. Orsatti, F. Piazza, “GSM transceiver front-end circuits in 0.25-μm CMOS,” IEEE J. Solid-State Circuits, Vol. 34, No. 3, pp. 292-303, Mar. 1999.

[24]T. Soorapanth and T.H. Lee, “RF linearity of short-channel MOSFETs,” Proceedings of 1st international workshop on Design of mixed-mode integrated circuits and applications, Cancun, Mexico, pp. 81-84, 1997.

[25]K. L. Sullivan, B. A. Xavier, and W. H. Ku, “Low Voltage Performance of a Microwave CMOS Gilbert Cell Mixer,” IEEE J. Solid-State Circuits, Vol. 32, pp. 1151-1156, Jul. 1997.

[26]R. Ludwig and P. Bretchko, RF Circuit Design: Theory and Applications, Prentice-Hall, Inc., 2000.

[27]H. Hashemi, A. Hajimiri, “Concurrent Multiband Low-Noise Amplifier-Theory, Design, and Applications,” IEEE Tran. On Microwave Theory and Techniques, Vol. 50, No. 1, pp. 288-301, Jan 2002.

[28]M. Ben Amor, A. Fakhfakh, H. Mnif, M. Loulou, “Dual Band CMOS LNA Design With Current Reuse Topology,” in DTIS, pp. 57 – 61, 2006.

[29]H. Hashemi and A. Hajimiri, “Concurrent Multi-band Low-Noise Amplifier-Theory, Design, and Ap-plications,” IEEE Trans. On Microwave Theory Tech., vol.50, no.1, Jan. 2001.

[30]Liang-Hung Lu, Hsieh-Hung Hsieh, and Yu-Shun Wang, “A Compact 2.4/5.2-GHz CMOS Dual-Band Low-Noise Amplifier,” IEEE Microwave and Wireless Components Letters, Vol. 15, No. 10, Oct. 2005

校內：2008-11-06公開
校外：2008-11-06公開

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