類比乘法器至今已被用於許多的應用上，像是:通訊調變、影像處理。乘法器通常需要與其他電路做結合，因此與其他電路之相容性對於一個乘法器來說非常重要。基於此，本論文提出一個全新架構的乘法器，此乘法器能實現兩個電壓之間的乘法運算，且將結果直接轉為數位輸出。換句話說，此架構之乘法器結合了一個類比乘法器與一個類比數位轉換器(Analog-to-Digital Converter)的功能。
本晶片採用台灣積體電路公司(TSMC)0.18μm 1P6M混和訊號製程製作，以32 S/B封裝，包含PAD部分的晶片總面積為953×823 μm2。此電路量測平均誤差在0.89%、最大誤差為1.63%。此外，在1.8V之靜態功耗為252μW、最大功耗為486μW。

Analog multipliers have been utilized in many applications, such as modulators and image processing. Since the multipliers are usually integrated with other digital circuits, an analog-to-digital converter (ADC) is commonly used to convert its analog output signal to digital codes. Therefore, a novel architecture of analog multiplier is proposed in this thesis. The proposed multiplier can realize a multiplying function of two voltages and directly convert the result into digital codes. In other words, it combines the functions of an analog multiplier and an ADC.

The proposed chip was fabricated by TSMC 0.18μm 1P6M CMOS/MEMS mixed signal process, and the chip size is 953×823 μm2. The average error of measurement result is 0.89%. The maximal error of measurement result is 1.63%. Moreover, the quiescent and maximum power consumptions are 252μW and 486μW at 1.8V, respectively.

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