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研究生： 蔡慧嫺
Tsai, Hui-Hsien
論文名稱： 具可測試性架構之整合H.264/AVC二維轉換設計
Integrated 2-Dimensional Transform Designs with Design-for-Testability Scheme in H.264/AVC
指導教授： 楊家輝
Yang, Jar-Ferr
劉濱達
Liu, Bin-Da
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2007
畢業學年度： 95
語文別： 英文
論文頁數： 59
中文關鍵詞： 二維轉換 、測試性 、H.264
外文關鍵詞： H.264, 2-Dimensional Transform, testable
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    • 本論文主旨在於有效率地實現影像系統當中的離散餘弦轉換及使其能有自我測試的功能，其中包含了兩個部分，在第一個部分當中，我們針對目前H.264/AVC視訊壓縮標準的最高等級(high profile)，提出了一個彈性的離散餘弦轉換架構。此架構能有效地將所有反轉換的電路架構整合在一起，並適用於H.264/AVC各等級的解碼器。此架構是利用 0.18 m之互補式金氧半製程技術，其合成的結果顯示，最快的時脈速度可達到125 MHz，可符合現行所有影像畫面所需的處理速度。而在第二部分當中，我們先針對H.264標準所訂定大小為4×4的轉換設計了一個有效測試的硬體架構。此架構是用C-testability的觀念來實現，較適用於規則性的硬體，用其觀念找出自我測試樣本，而此測試樣本並不會因為硬體架構的大小而有所改變。此架構只需八組測試樣本，就可以針對single stuck-at fault 測試模型，達到百分百的錯誤覆蓋率。

    This thesis focuses on the efficient implementation of the transform coding with Design-for-Testability capability in video coding systems, including two parts. In the first part, we aim a flexible inverse transform structure at the high profile in H.264/AVC. This architecture is efficiently combined all inverse transforms together and suitable for all profile in H.264/AVC decoder. The proposed structure is synthesized with 0.18 m CMOS technology. The synthesized flexible transform architecture achieves 125 MHz clock frequency. In the second part, we firstly design a 2-D 4×4 transform architecture with a Design-for-Testability scheme for H.264/AVC. Its architecture is implemented by C-testability which fits for the more regular circuits with a constant test set regardless of the circuit size. The proposed architecture just needs eight test patterns for single stuck-at fault model to achieve 100% fault coverage.

    Abstract v Acknowledgement vii Table of Contents viii List of Tables x List of Figures xi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of the Thesis 3 Chapter 2 Basic Concepts for 2-D Transforms and Design-for-Testability Schemes 4 2.1 Basic Concepts for 2-D Transforms in H.264/AVC 4 2.2 Design-for-Testability Schemes 10 2.2.1 M-testability approach 11 2.2.2 C-testability approach 13 Chapter 3 Transform Architectures in H.264 Advanced Video Coding 15 3.1 4×4 Transforms Architectures 16 3.1.1 Forward transform architectures 17 3.1.2 Inverse transform architectures 21 3.1.3 Multiple transform architectures 24 3.2 Flexible Architecture for All Transforms in H.264/AVC Decoder 25 3.2.1 Flexible transform architecture 26 3.2.2 4×4 Inverse integer transform 27 3.2.3 Inverse Hadamard transform 28 3.2.4 8×8 Inverse transform 30 3.2.5 Overall architecture 31 Chapter 4 Efficient Design-for-Testability Scheme for 2-D Transform in H.264 A Advanced Video Coders 34 4.1 C-Testable Full-Adder 35 4.2 C-Testable 2-D Transform 37 4.2.1 Single Cin test signal 38 4.2.2 Four Cin test signals 40 Chapter 5 Simulation Results and Verification 44 5.1 Simulation Results for Flexible Transform Architecture 45 5.2 Simulation Results and Comparisons for the DfT Scheme 47 5.3 Verification 50 5.4 Summary 52 Chapter 6 Conclusions and Future Work 53 6.1 Conclusions 53 6.2 Future Work 54 References 56 Publications 59 Award 59

    [1] ITU-T Recommendation H.264 & ISO/IEC 14496-10 AVC, Advanced Video Coding for Generic Audiovisual Services, version 3, 2005.
    [2] I. Amer, W. Badawy, and G. Jullien, “A high-performance hardware implementation of the H.264 simplified 8×8 transformation and quantization,” in Proc. IEEE ICASSP, Mar. 2005, pp. 1137-1140.
    [3] L. Agostini, R. Porto, J. Guntzel, and I. S. Silva, “High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard,” in Proc. IEEE ISCAS, May 2006, pp. 5419-5422.
    [4] W. T. Cheng and J. H. Patel, “A minimum test set for multiple fault detection in ripple carry adders,” IEEE Trans. On Computers, vol. C-36, pp. 891-895, July 1987.
    [5] Z. Y. Cheng, C. H. Chen, B. D. Liu, and J. F. Yang, “High throughput 2-D transform architectures for H.264 advanced video coders,” in Proc. IEEE APCCAS, Dec. 2004, pp. 1141-1144.
    [6] K. H. Chen, J. I. Guo, and J. S. Wang, “A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264,” IEEE Trans. Circuits Syst. Video Technol., vol. 16, pp. 472-483, Aug. 2006.
    [7] H. Elhuni, A. Vergis, L. Kinney, “C-testability of two-dimensional iterative arrays,” IEEE Trans. Computer-Aided Design, vol. 4, pp. 573-681, Oct. 1986.
    [8] C. P. Fan, “Fast 2-dimensional 4×4 forward integer transform implementation for H.264/AVC,” IEEE Trans. Circuits Syst. Ⅱ, vol. 53, pp. 174-177, Mar. 2006.
    [9] C. P. Fan, “Cost-effective hardward sharing architectures of fast 8×8 and 4×4 integer transforms for H.264/AVC,” in Proc. IEEE APCCAS, Dec. 2006, pp. 776-779.
    [10] S. Gordon, D. Marple, and T. Wiegand, “Simplified use of 8x8 transforms – updated proposal and results,” JVT-K028, 11th Meeting, Munich, Germany, 15-19 March, 2004.
    [11] T. Haniotakis, Y. Tsiatouhas, and D. Nikolos, “C-testable one-dimensional ILAs with respect to path delay faults: theory and applications,” in Proc. IEEE DFTVS, Nov. 1998, pp. 155-163.
    [12] A. Hallapuro, M. Karczewicz, and H. S. Malvar, “Low complexity transform and quantization,” in Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, Docs. JVT-B038 and JVT-039, Jan. 2002.
    [13] H. B. Kim, and D. S. Ha, “Design and synthesis of built-in self-testable two-dimensional discrete cosine transform circuits,” in Proc. IEEE ASIC, Sept. 2000, pp. 3-7.
    [14] S. K. Lu, C. W. Wu, and S. Y. Juo, “ Design of easily testable VLSI arrays for discrete cosine transform,” in Proc. ACSSC, Oct. 1992, pp. 989-993.
    [15] H. Y. Lin, Y. C. Chao, C. H. Chen, B. D. Liu, and J. F. Yang, “Combined 2-D transform and quantization architectures for H.264 video coders,” in Proc. IEEE ISCAS, May 2005, pp. 1802-1805.
    [16] H. S. Malvar, A. Hallapuro, M. Karczewicz, and L. Kerofsky, “Low-complexity transform and quantization in H.264/AVC,” IEEE Trans. Circuits Systs. Video Technol., vol. 13, pp. 598-603, July 2003.
    [17] D. E. Popescu, and C. Popescu, “The C-testability analysis of the superblock carry-lookahead adder (SBCLA),” in Proc. MWSCAS, Aug. 2002, pp. 469-472.
    [18] D. E. Popescu, and C. Popescu, “A minimal testing technique for single stuck-at faults in a pyramidal carry lookahead adder (PyCLA),” in Proc. MWSCAS, July 2004, pp. 439-442.
    [19] A. Rubio, R. Anglada, and J. Figueras, “Easily testable iterative unidimensional CMOS circuits,” in Proc. European Test Conference, Apr. 1989, pp. 240-245.
    [20] M. B. I. Reaz, and S. Z. Islam, “VHDL modeling of built-in-self-test (BIST) for system on chip (SOC) design,” in Proc. IEEE ICSE, Dec. 2002, pp. 222-225.
    [21] I. E. G. Richardson, H.264 and MPEG-4 Video Compression: Video Coding for Next Generation Multimedia. Chichester, UK: John Wiley & Sons, 2003.
    [22] M. D. Shieh, S. C. Shen, Y. C. Lin, and K. J. Lee, “Efficient testing and design-for-testability schemes for multimedia cores: a case study on DCT circuits,” in Proc. IEEE APCCAS, Dec. 2004, pp. 177-180.
    [23] T. C. Wang, Y. W. Huang, H. C. Fang, and L. G. Chen, “Parallel 4×4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264,” in Proc. IEEE ISCAS, May 2003, pp. 800-803.
    [24] T. Wiegand, G. J. Sullivan, G. Bjontegaard, and A. K. Luthra, “Overview of the H.264/AVC video coding standard,” IEEE Trans. Circuits Syst. Video Technol., vol. 13, pp. 560-576, July 2003.

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