在本篇論文中，介紹了一個整合類比數位轉換電路於單晶片的互補式金氧半影像感測器，影像感測器的設計規格為VGA，解析度640×480像素，輸出圖像速率為每秒三十張影像。每四行影像感測單元（Pixel）共用一個類比數位轉換器，且使用可消去固定圖像雜訊的二次取樣電路作為影像訊號擷取。類比數位轉換器使用單斜率架構因電路簡單可有效節省面積與功率消耗，並且具有良好的線性度表現。

　　包含影像感測器與二次取樣電路及十位元之類比數位轉換器的晶片實做使用供應電源為3.3伏特的TSMC 0.18μm 1P6M CMOS製程。在一般狀況下FFT模擬結果得到有效位元為9.2位元且功率消耗為88.6mW。每個像素大小為4μm×4μm，而晶片總面積為1.0176 mm2。全晶片包含單行64個影像感測單元、16個行類比數位轉換器、時脈產生電路、帶差電流源、十位元計數器、斜波訊號產生器及輸出級緩衝電路和接腳。

　A CMOS image sensor with ADC on-chip has been designed. The sensor fits VGA specification with 640×480 image sensor resolution and outputs 30 frames per second. Every four columns of image sensor share one ADC, and CDS circuits are used to sample voltage signals from the pixel array and convert it from analog to digital by the on-chip ADC. The output signal of each pixel is sampled by a Correlated-Double-Sampling circuit that is implemented with a switch-capacitor subtractor in order to eliminate fixed pattern noise and increase the accuracy. The ADC is designed using a single-slope A/D conversion topology with a high linearity and simple circuit structure to effectively reduce the chip area and power consumption.

　The implementation of the 10-bit ADC with a VGA pixel array and CDS circuits adopts TSMC 0.18μm 1P6M 3.3V CMOS technology. The FFT simulation results reveals ENOB of 9.2 bits for typical condition (TT, 55℃) and power consumption is 88.6 mW. The pixel size of the on-chip pixel array is 4μm×4μm. Total chip area is 1.0176 mm2 including 64 pixels in a row, 16 column ADCs, clock generator, bandgap current reference, 10-bit counter, ramp generator, output buffers, and pads.

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