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研究生: 邱于展
Chiu, Yu-Chan
論文名稱: 具輸出級窄波消除技術之低電磁干擾高傳真D類放大器
A Low-EMI High-fidelity Class-D Amplifier with Output Stage Narrow Pulse Elimination
指導教授: 郭泰豪
Kuo, Tai-Haur
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2022
畢業學年度: 110
語文別: 英文
論文頁數: 118
中文關鍵詞: 混疊失真音頻放大器D類放大器電磁干擾窄波脈寬調變總諧波失真加雜訊
外文關鍵詞: Aliasing distortion, audio amplifier, Class-D amplifier, electromagnetic interference (EMI), narrow pulse, pulse-width modulation (PWM), total harmonic distortion plus noise (THD+N)
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  • D 類放大器藉由切換開關的方式可達到卓越的功率效率,因此被廣泛應用於各種 音頻應用,然而輸出級的切換開關操作不可避免地產生了電磁干擾,採用 CMFBD 調 變是降低共模電磁干擾有效的方法,但是其在小輸入時會產生窄波,將於低輸出功率範圍顯著地增加總諧波失真加雜訊。本論文針對類比輸入閉迴路架構的 D 類放大器,提出一個應用於 CMFBD 輸出級的窄波消除技術,此外,本論文亦採用具三電平前饋路徑之頻率等化脈寬調變殘餘混疊失真抑制技術,因此,在整體輸出功率範圍下總諧波失真加雜訊可被大幅減少,同時兼具良好的共模電磁干擾抑制效果。
    本論文之 D 類放大器晶片實現於 TSMC 0.18 微米技術,由 pre-layout 模擬結果顯示,本論文在 5 伏特之電源電壓及 8 歐姆負載下可達到 0.00075%之最低總諧波失真加雜訊且僅消耗 1.1 毫安培之靜態電流,此外,在使用所提出之窄波消除技術下,動態範圍及低輸出功率範圍之總諧波失真加雜訊皆可大幅改善達 15 dB。與現有最佳文獻之 D 類音頻放大器相比,可達具競爭力之動態範圍 107 dB。

    Class-D amplifiers are widely used in various audio applications since they achieve superior power conversion efficiency by their switching behavior. However, the presence of switching activity at the output stage inevitably generates electromagnetic interference (EMI). Adopting common-mode-free BD (CMFBD) modulation is an effective way to reduce common-mode (CM) EMI, but it produces narrow pulses when a small input is applied, significantly increasing the total harmonic distortion plus noise (THD+N) in the low output power (POUT) range. In this thesis, a narrow pulse elimination (NPE) technique for the CMFBD output stage is presented for analog-input closed-loop Class-D audio amplifiers. Furthermore, the frequency-equalized PWM-residual-aliasing reduction technique with a tri-level feedforward path is also adopted. Therefore, the THD+N over the entire POUT range can be greatly reduced with a well-suppressed CM EMI.
    Implemented in the TSMC 0.18-μm process, the pre-layout simulation shows that this work’s Class-D amplifier achieves the minimal THD+N of 0.00075% while consuming a low quiescent current of 1.1 mA with a supply of 5 V and a speaker load of 8 Ω. In addition, with the presented NPE technique, both the dynamic range and the THD+N in the low POUT range are greatly reduced by 15 dB. Compared with state-of-the-art Class-D audio amplifiers, this work features the competitive dynamic range of 107 dB.

    摘要 I Abstract II Acknowledgment III Table of Contents IV List of Tables VI List of Figures VII Chapter 1. Introduction 1 1.1 Motivation 1 1.2 Organization 4 Chapter 2. Background of Class-D Amplifiers 5 2.1 Architecture and Modulation Scheme 5 2.1.1 Performance Indices 5 2.1.2 Linear Amplifier and Switching Amplifier 7 2.1.3 Pulse-Width Modulation (PWM) Scheme 10 2.2 Analysis of Power Loss and Distortion 15 2.2.1 Power Loss 15 2.2.2 Power Stage Distortion 18 2.2.3 PWM-Residual-Aliasing Distortion 23 2.3 Electromagnetic Interference (EMI) 29 2.3.1 EMI Regulations and Categories 29 2.3.2 Prior Arts of EMI Reduction 34 2.4 Limitations in Prior Realization of CMFBD Modulation 39 2.4.1 Sensitivity to Gate Driver Timing 39 2.4.2 Output Common-Mode Spikes 42 2.4.3 Narrow Pulses in Low Output Power Range 44 CHAPTER 3. System Design 46 3.1 CMFBD Modulation with Narrow Pulse Elimination 46 3.1.1 Prior Arts for Narrow Pulse Issue 47 3.1.2 Discussion of Various Patterns for Narrow Pulse Compensation 51 3.1.3 Design of Presented Narrow Pulse Elimination 70 3.2 FE-PRAR Technique with Tri-level Feedforward Path 74 3.2.1 Prior FE-PRAR Technique [16][18] 74 3.2.2 Analysis and Realization of Presented FE-PRAR Technique 76 3.2.3 Design of Presented FE-PRAR Loop Filter 81 Chapter 4. Circuit Implementation 87 4.1 Narrow Pulse Elimination Circuit for CMFBD Power Stage 87 4.1.1 Narrow Pulse Compensation Logic 88 4.1.2 Narrow Pulse Detection-and-Enable Logic 91 4.1.3 CMFBD Power Stage 93 4.2 Tri-level Feedforward Circuit for FE-PRAR Loop Filter 99 4.2.1 Tri-level Feedforward Circuit 99 4.2.2 PWM Modulator 100 4.2.3 FE-PRAR Loop Filter 101 Chapter 5. Layout and Simulation Results 103 5.1 Layout Floor Plan 103 5.2 Simulation Result 104 5.3 Performance summary 108 Chapter 6. Conclusion and Future Work 109 6.1 Conclusion 109 6.2 Future Work 109 References 110 Appendices 114

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