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研究生: 胡士皇
Hu, Shih-Huang
論文名稱: 針對異質系統中介語言繪圖處理器之具有架構導向的複合式功率模型
An Architecture-Aware Hybrid Power Model for a Heterogeneous-System-Architecture-Intermediate-Language Conformed GPU
指導教授: 邱瀝毅
Chiou, Lih-Yih
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2017
畢業學年度: 105
語文別: 中文
論文頁數: 44
中文關鍵詞: 功率模型繪圖處理器架構探勘功率管理
外文關鍵詞: Power model, Graphic processing unit (GPU), Architecture exploration, Power management.
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  • 近年來繪圖處理器的運算能力隨著核心堆疊而快速的上升,使用繪圖處理器加速的異質運算系統崛起,例如手機多媒體晶片或高效能計算領域,比傳統系統架構能有數十倍至數百倍的效能提升,但隨之而來的高功耗與熱累積需要花更多的散熱預算,因此需要針對繪圖處理器的能源效率進行建模與改善。
    本論文提出架構導向之繪圖處理器功率模型,與行為模型結合成一系統層級繪圖處理器設計平台,早期的功率評估資訊可以幫助系統架構設計者在早期設計階段進行系統架構功率優化與功率管理演算法開發。此功率模型包含客製化指令集之流處理器與記憶體系統,由下而上的建模方法使其具有很大的模擬彈性與擴充性,開發者能夠在系統層級模擬平台上執行不同特性的測試程式,剖析繪圖處理器架構設計的運算效率議題。

    Nowadays, graphic processing unit (GPU) computing ability increases rapidly due to core stacking. Heterogeneous computing systems are popular using an GPU as an accelerator, such as multi-media SoC and high performance computing applications. It can achieve stronger performance and higher energy efficiency when compared with conventional CPU-based systems. Consequently, high energy consumption and heat problem need to be taken care.

    In this work, we propose an architecture-aware GPU power model that can be combined with an HSAIL-conformed GPU simulator. It can provide power information to optimize power consumption at early stage of design and assist to develop power management algorithms. The model contains streaming processors with a customized instruction set and a memory system. Bottom-up power modeling provides great flexibility and extensibility that allow developers to evaluate the energy efficiency for architecture exploration.

    摘 要 i 誌 謝 vi 目錄 vii 表目錄 ix 圖目錄 x 第1章 緒論 1 1.1 研究動機 3 1.2 研究貢獻 4 1.3 論文架構 4 第2章 相關研究背景 5 2.1 繪圖處理器 5 2.2 功率模型概觀 7 2.2.1 電子系統層級平台之功率模型 7 2.2.2 功率模型層級 9 2.2.3 功率最佳化 10 2.3 異質系統架構 11 第3章 相關文獻探討 14 3.1 利用McPAT建立繪圖處理器功率模型 14 3.1.1 MacSim之功率模型 15 3.1.2 GPGPU-Sim之功率模型:GPUWattch 17 3.2 基於指令層級之繪圖處理器能量模型 19 第4章 架構導向之功率模型建立 22 4.1 問題描述 22 4.2 目標虛擬平台架構 24 4.3 繪圖處理器複合式功率模型 26 第5章 實驗結果與分析 33 5.1 實驗環境設定 33 5.2 實驗一、運算單元建模方法準確度驗證 34 5.3 實驗二、流處理器功耗趨勢分析 36 5.4 實驗三、功率最佳化分析 38 第6章 結論與未來研究 40 6.1 結論 40 6.2 未來工作 41 參考文獻 42

    [1] J. Leng, T. Hetherington, A. ElTantawy, S. Gilani, N. S. Kim, T. M. Aamodt, and V. J. Reddi, “GPUWattch: Enabling Energy Optimizations in GPGPUs,” in Proc. 40th Annu. Int. Symp. Comput. Archit. - ISCA ’13, vol. 41, p. 487, 2013.
    [2] J. Lim, N. B. Lakshminarayana, H. Kim, W. Song, S. Yalamanchili, and W. Sung, “Power Modeling for GPU Architectures Using McPAT,” ACM Trans. Des. Autom. Electron. Syst., vol. 19, no. 3, pp. 1–24, 2014.
    [3] S. Hong and H. Kim, “An integrated GPU power and performance model,” in Proc. 37th Annu. Int. Symp. Comput. Archit. - ISCA ’10 , vol. 38, no. 3, p. 280, 2010.
    [4] University of British Columbia. “GPGPU-Sim 3.1.1 Manual,” 2012. [Online]. Available: http://gpgpu-sim.org/manual/index.php/Main_Page.
    [5] C. Isci and M. Martonosi, “Runtime power monitoring in high-end processors: Methodology and empirical data,” in Proc. Annu. Int. Symp. Microarchitecture, MICRO, vol. 2003–Janua, pp. 93–104, 2003.
    [6] NVIDIA Corporation, “NVIDIA’s Next Generation CUDA Compute Architecture: Fermi,” 2009. [Online]. Available: http://www.nvidia.com/content/PDF/fermi_white_papers/P.Glaskowsky_NVIDIA's_Fermi-The_First_Complete_GPU_Architecture.pdf
    [7] HSA Foundation, “HSA Programmer's Reference Manual: HSAIL Virtual ISA and Programming Model, Compiler Writer, and Object Format (BRIG) Version 1.0 Final,” 2015.
    [8] HSA Foundation, “HSA Platform System Architecture Specification Version 1.0 Final,” 2015.
    [9] Y. Wang and N. Ranganathan, “An instruction-level energy estimation and optimization methodology for GPU,” in Proc. - 11th IEEE Int. Conf. Comput. Inf. Technol. CIT 2011, pp. 621–628, 2011.
    [10] A. Marmin, C. H. Lai, H. Tago, H. L. Huang, and J. M. Lu, “Architecture agnostic energy model for GPU-based design,” in Proc. Int. Symp. VLSI Des. Autom. Test, pp. 0–3, 2016.
    [11] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A Tool to Model Large Caches,” HP Laboratories, Tech. Rep. HPL-2009-85, 2009.
    [12] S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi, “McPAT 1.0: An Integrated Power, Area, and Timing Modeling Framework for Multicore Architectures,” in Proc. 42nd Annu. Int. Symp. Microarchitecture, MICRO, pp. 469–480, 2009.
    [13] R. A. Bridges, N. Imam, and T. M. Mintz, “Understanding GPU Power: A Survey of Profiling, Modeling, and Simulation Methods,” ACM Comput. Surv., vol. 49, no. 3, pp. 1–27, 2016.
    [14] H-Y. Chen, “An HSAIL ISA Conformed GPU Platform,” the thesis for Master of Science. National Cheng Kung University, Tainan, Taiwan. 2015.
    [15] N. Kroupis and D. Soudris, "FILESPPA: fast instruction level embedded system power and performance analyzer," J. Microelectromech. Syst., vol. 35, no. 1, pp. 329-342, Feb. 2011.
    [16] H. Kim, J. Lee, N. B. Lakshminarayana, J. Sim, J. Lim, and T. Pho, “MacSim : A CPU-GPU Heterogeneous Simulation Framework,” 2012. [Online]. Available: http://comparch.gatech.edu/hparch/macsim/macsim.pdf
    [17] S. Hong and H. Kim, “An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness,” ACM SIGARCH Comput. Archit. News, vol. 37, no. 3, p. 152, 2009.
    [18] K. Chandrasekar, B. Akesson, and K. Goossens, “Improved power modeling of DDR SDRAMs,” in Proc. - 14th Euromicro Conf. Digit. Syst. Des. Archit. Methods Tools, DSD 2011, pp. 99–108, 2011.
    [19] O. Naji, C. Weis, M. Jung, N. Wehn, and A. Hansson, “A High-Level DRAM Timing , Power and Area Exploration Tool,” in Proc. - Embed. Comput. Syst. Archit. Model. Simul., SAMOS 2015, pp. 149–156, 2015.
    [20] NVIDIA, “NVIDIA’s Netx Generation CUDA Compute Architecture: Kepler GK110,” pp. 1–24, 2012. [Online]. Available: https://www.nvidia.com/content/PDF/kepler/NVIDIA-Kepler-GK110-Architecture-Whitepaper.pdf
    [21] Semiconductor Industries Association, “Model for Assessment of CMOS Technologies and Roadmaps (MASTAR),” 2007. [Online]. Available: http://www.itrs2.net/itrs-models-and-papers.html
    [22] W-S. Hsieh, “Micro-Architecture Optimization of HSA-Compatible GPU,” the thesis for Master of Science. National Cheng Kung University, Tainan, Taiwan. 2016.
    [23] S. Song, C. Su, B. Rountree and K. W. Cameron, "A Simplified and Accurate Model of Power-Performance Efficiency on Emergent GPU Architectures," in Proc. International Symposium on Parallel and Distributed Processing, pp. 673-686, 2013.
    [24] NVIDIA, “CUDA C PROGRAMMING GUIDE,” 2017. [Online]. Available: http://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html

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