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研究生: 林安傑
Lin, An-Jie
論文名稱: 對新色彩深度解包裝之深度圖像生成與VLSI實現
Depth Image-Based Rendering and Its VLSI Implementation for New Video and Depth De-packing
指導教授: 劉濱達
Liu, Bin-Da
楊家輝
Yang, Jar-Ferr
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2014
畢業學年度: 102
語文別: 英文
論文頁數: 61
中文關鍵詞: 幀兼容包裝格式三維視訊深度圖像生成法
外文關鍵詞: Frame compatible, Packing format, 3D video, DIBR
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  • 本論文提出一種對於新色彩深度解包裝之深度圖像生成的硬體架構實現。相較於一般的幀兼容格式,新色彩深度包裝格式對於彩圖以及深度圖在垂直方向皆將採樣降至四分之三的解析度再進行處理,當此格式解包裝時,則需對於彩圖以及深度圖在垂直方向做採樣提升。
    本硬體架構採用Lanczos濾波器來進行兩階段的升採樣和降採樣。為了簡化硬體實現起見,本論文將濾波器的係數調整為以移位方式就可達成的係數。藉由十二列的記憶體空間,將每三個垂直方向的像素升採樣為四個像素,而經由深度圖像生成演算法,解包裝後的影像可生成出不同視角之虛擬影像。
    硬體架構方面,本設計以TSMC 0.18 μm製程合成的結果,共需要6.34 k個邏輯閘,系統操作頻率可達到100 MHz,可支援包裝影像格式至1920 × 1088,而解包裝後影像之峰值信噪比平均值可達到41 dB。

    In this thesis, a hardware architecture of depth image-based rendering (DIBR) for new video and depth de-packing is proposed. Unlike the format of one view plus one depth, the advanced 2D compatible format reduces the bitrates of both color and depth frames.
    In the proposed architecture, the Lancos filter is adopted for the proposed two-stage resizing. For hardware implementation, the coefficients of lanczos filter are modified to the coefficients which can be achieved by shifting. For every three pixels in vertical direction, total twelve line buffers are used to store the information and output four pixels. Then the DIBR system can synthesize the other viewpoints for the 3D display.
    Simulation result shows that the proposed system requires 6.34k gates. The proposed architecture can achieve 100 MHz. The maximum frame size achieves FHD (1920 × 1088). The proposed architecture achieves 41 dB in the average PSNR.

    Abstract (Chinese) i Abstract (English) iii Acknowledgement v Table of Contents vii List of Figures ix List of Tables xi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of the Thesis 3 Chapter 2 Overview of Related Work 5 2.1 Depth Image-based Rendering System 5 2.1.1 3D warping 7 2.1.2 Hole filling 13 2.1.3 Depth map preprocessing 14 2.2 Compatible Video and Depth Packing Format 17 2.2.1 2D compatible vertical packing 18 Chapter 3 The Proposed Hardware Design of the De-packing Flow and DIBR System 23 3.1 Overview of the Proposed System 23 3.2 Filter Design 25 3.2.1 Up-sampling 26 3.2.2 Down-sampling 29 3.3 Optimization of the Memory Utilization 31 3.3.2 Memory utilization of filter design 33 3.3.3 Memory utilization of DIBR 36 3.4 Architecture of the Overall System 41 Chapter 4 Simulation Results and Discussion 43 4.1 Simulation Results 43 4.2 Verification 52 Chapter 5 Conclusions and Future Work 53 5.1 Conclusions 53 5.2 Future Work 54 References 57 Biography 61

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