在過去，我們實驗室曾經提過一個具有掃描鍊與邏輯陣列的測試晶片架構，同時提出了診斷該架構下存在的靜態錯誤，包括固定型故障錯誤、輸入向量錯誤、橋接錯誤。而在我們這篇論文中，我們會在同樣的架構下去提出一個診斷流程來診斷傳輸延遲錯誤。該流程包括兩個測試方法，而在100MHz的ATE操作下，所需的執行時間在不同規格的測試晶片中僅需不到1秒的時間。在單一錯誤假設下，估算結果顯示該方法具有100%的平均診斷率;而在雙錯誤假設下，估算結果顯示該方法對單錯誤具有89.982%的平均診斷率而對雙錯誤具有99.961%的平均診斷率。而我們的工作除了電路中的傳輸延遲錯誤，也考慮到掃描鏈上的傳輸延遲錯誤。因此錯誤被診斷出來時也能反映出掃描鏈上與時間有關的缺陷。

In the past, our laboratory proposed the scan-based logic array test chip architecture and has proposed a method to diagnose static faults under this architecture, including stuck-at fault (SAF), Input Pattern Fault (IPF), Bridging Fault (BF). In this work, we propose a diagnosis flow on the same architecture to diagnose transition delay fault. The procedure consists of two tests, and the required time for test chips with various specifications is less than 1 second when executing the procedure on 100MHz ATE. Under the single fault assumption, evaluation results show that the proposed procedure can achieve 100% average diagnosability. Under the double fault assumption, it can achieve 89.982% for single faults and 99.961% for double faults. In addition to the TDFs of the circuit, we also consider TDFs in scan chains. Hence the faults diagnosed by the procedure can reflect possible time-related defects in scan chains.

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