隨著半導體製程的進步，單晶片系統設計逐漸成為積體電路系統最重要的設計方法。然而，此種設計方法遭遇了許多嚴峻的問題，其中之一便是單晶片系統測試。而以嵌入式處理器為基礎的測試平臺技術已漸成為解決此問題最有效率方法之一，其主要原因在於測試平臺具低成本、高效率之特性，且可支援多種測試方法，包含了掃瞄測試、階層式測試與記憶體內建自我測試等。
在本篇論文中，我們針對一個典型之單晶片系統測試平臺，發展出一可應用於此測試平臺之設計自動化系統，名為DASTEP。DASTEP主要用於幫助使用者架構此一測試平臺並整合智財電路至此平臺上。為了標準化測試程序，DASTEP提供對智財電路包覆符合IEEE 1149.1及1500 標準之包裝表面。針對單晶片系統中的測試存取機制，DASTEP能自動產生一測試存取機制控制器(TAM controller)與相對應的測試匯流排(test bus)。DASTEP亦有合適的模擬環境用以執行完整測試流程並驗證使用者的電路設計與測試排程。另外，DASTEP提供友善的使用者介面以完成前述功能。綜合上述特性，DASTEP成為一關於單晶片系統測試，強大但仍極易使用的電子設計自動化系統。

In this thesis, a design automation system, called DASTEP, to help a user build a test platform and incorporate his/her designs into the platform is presented. DASTEP provides an interactive mode to allow the user to modify IP cores into testable ones and integrate them into the test platform. To standardize the test procedure, DASTEP furnishes the capability of wrapping the cores with the 1149.1 or 1500 standard wrappers. A sophisticated test-access-mechanism (TAM) controller along with the required test bus can be automatically synthesized which form the kernel of the test platform. DASTEP also creates appropriate simulation environment that allows the simulation of the entire test flow, making the verification of both core design and test plan possible. All the capabilities of DASTEP are provided via friendly graphic user interface, which makes DASTEP a powerful, yet very easy-to-use electronic design automation (EDA) system for SOC testing.

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