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研究生： 黃冠穎
Huang, Guan-Ying
論文名稱： 逐漸趨近式類比至數位轉換器之易於整合與有效利用能量設計技術
Easily-Integrated and Energy-Efficient Design Techniques for Successive-Approximation Analog-to-Digital Converters
指導教授： 張順志
Chang, Soom-Jyh
學位類別： 博士
Doctor
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2013
畢業學年度： 101
語文別： 英文
論文頁數： 92
中文關鍵詞： 逐漸趨近式類比數位轉換器 、有效利用能量類比數位轉換器 、易於整合之類比數位轉換器
外文關鍵詞： SAR ADC, ADC, successive approximation analog-to-digital converter, energy-efficient ADC, easily-integrated ADC
相關次數： 點閱：142  下載：33 
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    • 本論文提出四個應用於逐漸趨近式類比至數位轉換器的電路設計技術，並且透過實際的晶片下線和量測驗證，證實所提出之電路設計技術可以降低前端訊號緩衝器與參考電壓緩衝器的設計困難度同時提升逐漸趨近式類比數位轉換器的效能。所提出的電路設計技術以及晶片實作成果簡述如下：
    第一個技術是一個降低輸入負載的技術，實現在一個十位元的逐漸趨近式類比數位轉換器採用0.13-um互補式金氧半電晶體製程。與傳統的逐漸趨近式類比數位轉換器比較起來，此技術可以把一個十位元的逐漸趨近式類比數位轉換器的輸入負載降低到1.2 pF。在1.2 V的操作電壓與每秒取樣一千兩百萬次的操作速度下，此類比數位轉換器消耗0.32 mW且達到了50.89 dB的SNDR，等效的FOM為95 fJ/conversion-step。
    第二個技術為一個有效利用能量的回復式切換技巧，應用於一個十位元每秒取樣三千萬次的逐漸趨近式類比數位轉換器。與單調式切換技巧比較起來，此切換技巧可以降低輸入共模電壓的漂移，藉此來改善比較器的動態偏移電壓與寄生電容變化量。此回復式切換技巧在第一次切換數位類比轉換器的過程中並不會消耗任何的功率，可以降低參考電壓緩衝器的設計難度。此類比數位轉換器實現於90-nm 1P9M互補式金氧半電晶體製程，在1 V的操作電壓與每秒取樣三千萬次的操作速度下，此類比數位轉換器消耗0.98 mW，SNDR為56.89 dB，等效的FOM為57 fJ/conversion-step。
    第三個技術則是適用於生醫系統的跳躍式視窗技術。此技術主要的構想是，當訊號差小於所預定的跳躍式視窗，則跳過一些資料轉換的過程，以節省不必要的電容切換來節省功率消耗。如此一來，與傳統的逐漸趨近式類比數位轉換器比較起來，此技術可以同時節省電容式數位類比轉換器、比較器與數位控制電路的功率消耗。此外，跳躍式視窗還可以容忍電壓未穩定比較與比較器偏移電壓的問題，也可以降低DNL與INL的值。此類比數位轉換器實現於0.18-um 1P6M互補式金氧半電晶體製程，在0.6 V的操作電壓與每秒取樣二十萬次的操作速度下，此類比數位轉換器消耗1.04 um且達到57.97 dB的SNDR，等效的FOM為8.03 fJ/conversion-step，此類比數位轉換器所佔的面積為0.082 mm2。
    第四技術是結合了跳躍式視窗與直接切換技術，跳躍式視窗技術可以容忍DAC的不穩定比較錯誤且不需要額外的比較次數，而直接切換機制可以減少數位控制電路的延遲時間。此高速逐漸趨近式類比數位轉換器實現於40-nm 1P9M互補式金氧半電晶體製程，在0.9 V的操作電壓與每秒取樣兩億次的操作速度下，此類比數位轉換器消耗0.818 mW，SNDR為57.16 dB，等效的FOM為13.9 fJ/conversion-step，其所佔的面積為0.013 mm2。

    This dissertation presents four circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the proof-of-concept prototypes, the proposed techniques are able to reduce the design overhead of the front-end and reference buffer and improve the ADC performance. The proposed techniques and their associated chip measurement results are sketched as follows:
    The first technique is to develop a low input capacitance architecture for SAR ADCs. A 10-bit prototype is fabricated in 0.13-um CMOS process. Compared with conventional successive approximation ADCs, the proposed ADC can reduce the input capacitance to 1.2 pF for 10-bit resolution. At 12 MS/s and 1.2-V supply, this ADC consumes 0.32 mW and achieves an SNDR of 50.89 dB, resulting in a figure of merit (FOM) of 95 fJ/conversion-step.
    The second technique is a power efficient switchback switching method for a 10-bit 30-MS/s SAR ADC. With respect to the monotonic switching method, the proposed switching method can reduce the input common-mode voltage variation, which improves the dynamic offset and the parasitic capacitance variation of the comparator. In addition, the switchback switching method does not consume any power at the first DAC switching, which can reduce the power consumption and design effort of the reference buffer. The prototype was fabricated in 90-nm 1P9M CMOS technology. At 1-V supply and 30 MS/s, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 56.89 dB and consumes 0.98 mW, resulting in a FOM of 57 fJ/conversion-step.
    The third technique presents a bypass window SAR ADC for biomedical applications. To reduce energy consumption, a bypass window technique is used to select switching sequences to skip several conversion steps when the signal is within a predefined small window. The power consumptions of the capacitive DAC, latch comparator, and digital control circuit of the proposed ADC are lower than those of a conventional SAR ADC. The proposed bypass window tolerates the DAC settling error and comparator voltage offset in the first four phases and suppresses the peak DNL and INL values. A proof-of-concept prototype was fabricated in 0.18-um 1P6M CMOS technology. At 0.6-V supply voltage and 200-kS/s sampling rate, the ADC achieves a SNDR of 57.97 dB and consumes 1.04 uW, resulting in a figure of merit of 8.03 fJ/conversion-step. The ADC core occupies an active area of only 0.082 mm2.
    The fourth one, which combines the bypass window and the direct switching techniques, is manipulated to develop a high speed SAR ADC. The bypass window technique can tolerate the incomplete settling error of the DAC without any extra comparison cycle and the direct switching technique can reduce the digital circuit delay. The prototype was fabricated in 40-nm 1P9M CMOS technology. At 0.9-V supply voltage and 200-MS/s sampling rate, the ADC achieves a SNDR of 57.16 dB and consumes 818 uW, resulting in a figure of merit of 13.9 fJ/conversion-step. The ADC core occupies an active area of only 0.013 mm2.

    Abstract III Table of Contents V List of Tables VII List of Figures VIII Chapter 1 Introduction 1 1.1 MOTIVATION 1 1.2 DESIGN CHALLENGES OF SAR ADCS 3 1.3 POWER REDUCTION OF SAR ADCS 4 1.3.1 Total Capacitance Reduction 4 1.3.2 Power Efficient Switching Method 5 1.3.3 Small Unit Capacitor 6 1.4 CONVERSION RATE SPEEDED-UP OF SAR ADCS 7 1.5 ORGANIZATION OF THE DISSERTATION 10 Chapter 2 Easily-Integrated SAR ADC Design 12 2.1 INTRODUCTION 12 2.2 PROPOSED LOW INPUT CAPACITANCE SAR ADC 14 2.2.1 Conventional SAR ADC 14 2.2.2 Architecture of Low Input Capacitance SAR ADC 15 2.3 THE SWITCHBACK SWITCHING METHOD 17 2.3.1 Conventional Switching Method 17 2.3.2 Monotonic Switching Method 18 2.3.3 Proposed Switchback Switching Method 20 2.3.4 Switching Energy Analysis 21 2.4 A 10-BIT 12-MS/S LOW INPUT CAPACITANCE SAR ADC 25 2.4.1 Sample and Hold Circuit 25 2.4.2 Reference DAC 26 2.4.3 Comparator 27 2.4.4 Measured Results 28 2.5 A 10-BIT 30-MS/S SAR ADC WITH SWITCHBACK SWITCHING METHOD 33 2.5.1 Architecture 33 2.5.2 Sampling and Hold Circuit 34 2.5.3 SAR Control Logic 36 2.5.4 Measurement Results 37 2.6 SUMMARY 42 Chapter 3 Energy-Efficient SAR ADCs 43 3.1 INTRODUCTION 43 3.2 BYPASS WINDOW TECHNIQUE 45 3.2.1 Bypass Window Concept 45 3.2.2 Power Reduction of Different Window Size 46 3.2.3 Architecture of Proposed Bypass Window SAR ADC 49 3.2.4 Incomplete Settling Tolerance 50 3.2.5 Coarse Comparator Offset Tolerance 53 3.2.6 Power Reduction of Bypass Window 54 3.2.7 Linearity Improvement of Bypass Window 56 3.3 A 10-BIT 200-KS/S SAR ADC WITH BYPASS WINDOW TECHNIQUE 60 3.3.1 Dynamic Latch Comparator 60 3.3.2 Capacitive DAC 61 3.3.3 Digital Control Logic of Bypass Window SAR ADC 62 3.3.4 Reference Voltage of Bypass Window 64 3.3.5 Measured Results 66 3.4 A 10-BIT 200MS/S SAR ADC 72 3.4.1 Direct Switching Technique Combines with Bypass Window Technique 72 3.4.2 Architecture of Proposed SAR ADC 73 3.4.3 Architecture of Latch and Pulse Generator 74 3.4.4 Proposed Capacitor Cell 75 3.4.5 Measured Results 76 3.5 SUMMARY 80 Chapter 4 Conclusions and Future Work 81 4.1 CONCLUSIONS 81 4.2 FUTURE WORK 84 References 85 Publication List 90

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