本論文提出遞迴式架構，並共架構支援改良型離散餘弦和改良型離散正弦之正、逆轉換（MDCT/IMDCT/MDST/IMDST）。其演算法本質可支援MP3、AC-3、AAC等多種音訊規格。正因為支援多規格的情況下，一般傳統遞迴式的MDCT/ IMDCT/MDST/IMDST都需要記錄大量的係數，因而使用到不少的ROM。然而ROM的面積太大不利於多系統的整合，會使得應用的產品體積變大，有違現今世人對電子產品輕薄短小的要求。對此我們提出固定係數架構來達到免係數記憶體的需求。
另外使用CSD乘法器取代傳統乘法器，以進一步降低面積。此外還引入可調式係數的概念，一方面提高架構的精準度，一方面以低位元達高精準度的效用也變相的節省架構面積。再者，將其需要的排序動作以簡單的硬體實現，設計出不影響整系統速度硬體速度且無延遲的排序硬體。若欲支援更高規格，例如Twin VQ等，則可用兩套本論文的核心架構，在此情況下的面積仍佔有優勢，可兼顧速度和面積兩方。
在運算週期上，兩組核心硬體架的設計比起傳統設計最多可改善75%，單一核心硬體的設計比起傳統設計則可省50%；面積方面，核心硬體最多可以節省約58%的面積、和100%的ROM面積，降低硬體成本。綜合以上論點，本架構適合應用於支援多格式的多媒體系統。

This thesis presents a recursive architecture, that can support forward modified discrete cosine transform and modified sine cosine transform (MDCT/MDST), and its inverse (IMDCT/IMDST). This algorithm is essentially supports MP3, AC-3, AAC and other audio specifications. However, because of supporting various specifications, the conventional recursive MDCT, MDST, IMDCT, and IMDST need an amount of ROM to store the coefficient. Then, the bigger ROM size is, the more difficult to integrate is. And it leads to the large volume of the products, contrary to the requirements that electronics would be slim and light. Therefore, we proposed fixed coefficient architecture to achieve a free memory.
Also we replace the traditional multiplier with CSD multiplier, so that it reduces the area further. In addition, the thesis use the concept of the selectable coefficient, on the on hand to improve the accuracy of the structure, and the other hand it can use lower bit to get high-precision，that is also a form of saving area. Moreover, we implement the resort hardware simply, it doesn’t affect the speed of the all overall system, and there is no delay. If supporting a higher requirement standard, such as Twin VQ etc., we proposed two sets of the core structure. In this case, the implement area still has an advantage; it can take both speed and area into account.
In cycles, compared to traditional design, two sets core hardware can improve 75%, and single core hardware can improve 50%; in the area terms, the core hardware can save up to about 58% of the core area, and 100% of the ROM area, so that to reduce the hardware costs. Based on the above argument, the proposed architecture suitable for various format multimedia systems.

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