| 研究生: |
謝承燁 Hsieh, Cheng-Yeh |
|---|---|
| 論文名稱: |
應用於氣體感測之逐漸趨近式類比數位轉換器併讀取電路研製 Development of SAR ADC with Sensor Readout Circuits for Gas Sensing Application |
| 指導教授: |
王永和
Wang, Yeong-Her 吳伯昌 Wu, Po-Chang |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2021 |
| 畢業學年度: | 109 |
| 語文別: | 英文 |
| 論文頁數: | 68 |
| 中文關鍵詞: | 電阻轉電壓式讀取電路 、逐漸趨近式類比數位轉換器 、串連電容陣列 、校準電路 |
| 外文關鍵詞: | Resistance-to-voltage converter, Successive-approximation ADC, Series capacitors array, Calibration circuit |
| 相關次數: | 點閱:143 下載:0 |
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本論文整合電阻式感測讀取電路及逐漸趨近式類比數位轉換器的電路架構,可偵測極小電阻變化,並透過前述電路轉換為數位訊號做後續數據分析。本系統架構前端為電阻式感測器讀取電路,可偵測的電阻變化範圍為50-kΩ,並配備校準功能可抗溫度、濕度等環境因子,使系統可操作在非理想環境下。本系統架構後端為逐漸趨近式類比數位轉換器,具備二項優點。第一項為採用串連式電容陣列設計,可有效降低寄生電容影響,取得高精度轉換率。第二項為採用改良式全差動分段式架構,透過全差動方式,可有效降低雜訊;透過分段式架構將最高位及最低位電容陣列以耦合電容串聯,可有效降低布局面積;透過改良式架構使用單位電容做為耦合電容,可避免電容不匹配問題。本設計使用台積電 0.18-µm CMOS製程來實作晶片,晶片面積為933 × 980-μm2,操作電壓為1.8伏特及取樣速度為每秒一千四百萬次,總消耗功率為3.7-μW,有效位元數為8bits。
This paper integrates the resistive readout circuit with an analog-to-digital converter circuit. These combined circuits can detect very small changes in resistance and convert such changes into digital signals for subsequent data analysis. The front end of the combination circuits is a resistive readout circuit with a detectable resistance range of 50-kΩ that is equipped with a calibration mode to resist environmental factors such as temperature and humidity. Therefore, the system can work in a non-ideal environment. The back end of the combination circuits is a successive approximation analog-to-digital converter (A-D-C) circuit. The ADC circuit has two advantages: The first advantage is the use of a series capacitor array design that effectively reduces the influence of parasitic capacitance and reduces the layout area. The second advantage is the use of an improved fully differential segmented structure that effectively reduces noise. In addition, by using a unit capacitor as a coupling capacitor, the problem of capacitor mismatch can be avoided. The full circuit design utilizes TSMC’s 0.18-µm CMOS process to implement the chip, for which the chip area is 933 × 980-μm2. The operating voltage of this chip is 1.8 volts, and the operating speed reaches 14 million samples per second. The total power consumption is 3.7-µW, and the effective number of bits is 8 bits.
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