本論文提出一個低功耗且可以操作在奈奎斯模式跟超取樣模式的類比數位轉換器，目標為符合多種無線通訊規格，在奈奎斯模式這個類比數位轉換器是一個逐漸趨近式類比數位轉換器，它使用非同步控制及基於共模電壓切換機制，基於共模電壓切換機制可以達到較低的切換功耗，並藉由非同步控制，可以不需要仰賴快速的時脈產生器，只要用一些數位邏輯電路便可產生需要的時脈。
在另一個模態為一個錯誤回授式的三角積分調變器，它使用上面提到的逐漸趨近式類比數位轉換器為量化器，藉由逐漸趨近式類比數位轉換器的電容陣列在解完所有的數位碼時會儲存量化誤差，我們只需要一個運算放大器用來形成一個主動加法器就可以做到二階的雜訊移頻能力，這兩種模態操作在不同的取樣率且達成不同的規格。
本設計使用90奈米1P9M CMOS 製程去實現晶片，其核心電路面積為495μm × 486μm。從量測結果，這個類比數位轉換器可以操作在兩個模式且都達到不錯的功率效益，操作在50MS/s時，訊號雜訊失真比在逐漸趨近式類比數位轉換器是58.07dB，總共的功率消耗是0.882mW，DNL介於-1 LSB到+1.288 LSB，而INL介於-1.2 LSB到+1.445 LSB，在超取樣模式時，當操作在25MS/s，超取樣率為8時，最大可達到的訊號雜訊失真比是64.44dB，功率消耗為1.4mW，FOM在奈奎斯及超取樣模式各自達到34fJ/conv.和329fJ/conv.。

This thesis proposes a power-efficient dual-mode, i.e. Nyquist-rate mode and oversampling mode, analog-to-digital converter (ADC) for multiple specifications of wireless communication. Under Nyquist-rate operation, it is an asynchronous SAR ADC using the Vcm-based switching. The Vcm-based switching algorithm has the advantage of low switching power consumption. By using the asynchronous control, an on-chip fast clock generator is not necessary. Under the oversampling mode, it is an error-feedback sigma-delta modulator (SDM) which manipulates the above SAR ADC as the quantizer. Since the residue signal on the DAC array of SAR ADC is the quantization noise after bit cycling, the SDM just needs feedback the residue into an active adder to realize the second order noise-shaping ability. The two modes operate in different sampling rate and can be applied to two different specifications.
This work is fabricated in a 90nm 1P9M CMOS process. Its core area is 495μm × 486μm. From the measurement results, the ADC operating in the two modes can both achieve good power efficiency. The SNDR of the SAR ADC is 58.07dB at 50MS/s, and the total power consumption is 0.882mW. The DNL is between -1 LSB to +1.288 LSB, and the INL is between -1.2 LSB to +1.445 LSB. In the oversampling mode the oversampling ratio (OSR) is 8 and the ADC is operating in the sampling rate of 25MS/s, the peak SNDR is 64.44dB at 25MS/s. The power consumption is 1.4mW. The figure-of-merit (FOM) achieves 34fJ/conv. and 329fJ/conv. in Nyquist mode and oversampling mode respectively.

[1] A. Morgado, R. D. Rio, J. M. Rosa, Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio, Springer Science & Business Media, LLC 2011
[2] Y. Zhu, C. H. Chan, U. F. chio, S. W. Sin, S. P. U, R. P. Martins and F. Maloberti, “ A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, Jun. 2010.
[3] C. C. Liu, S. J. Chang, G. Y. Huang, Y. Z. Lin, “A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, pp. 731-740, Apr. 2010
[4] C. C. Liu, S. J. Chang, G. Y. Huang, Y. Z. Lin, C. M. Huang, C. H. Huang, “A 10b 100MS/s 1.13mW SAR ADC with Binary-Scaled Error Compensation,” ISSCC Dig. Tech. Papers, pp. 246-247, Feb., 2010.
[5] V. Hariprasath, J. Guerber, S. H. Lee and U. K. Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” Electron. Lett., vol. 46, no. 9, pp. 620-621, Apr. 2010.
[6] D. Johns and K. Martin, Analog Integrated Circuit Design. New York: John Wiley & Sons, 1997.
[7] B. Razavi, Principles of Data Converter System Design, New York: John Wiley & Sons, 1995.
[8] N. Maghari, S. Kwon, U. K. Moon, “74 db SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35dB Open-Loop Opamp Gain,” IEEE J. Solid-State Circuits, vol. 44, pp. 2212-2221, Aug. 2009
[9] A. Gharbiya, and D. A. Johns, “A 12-bit 3.125MHz Bandwidth 0-3 MASH Delta-Sigma Modulator,” IEEE J. Solid-State Circuits, vol. 44, pp. 2010-2018, Jul. 2009
[10] O. Rajaee, S. Takeuchi, K. Hamashita, U. K. Moon, “Low-OSR Over-Ranging Hybrid ADC Incorporating Noise-Shaped Two-Step Quantizer,” IEEE J. Solid-State Circuits, vol. 46, pp. 2458-2468, Nov. 2009
[11] J. Fredenburg, M. Flynn, “A 90MS/s 11MHz bandwidth 62dB SNDR noise-shaping SAR ADC,” ISSCC Dig. Tech. Papers, pp. 468-470, Feb., 2012.
[12] J. Silva, U. Moon, J. Steensgaard and G. C. Temes, “Wideband low-distortion delta-sigma ADC topology,” Electron. Lett., vol. 37, no. 12, pp. 737-738, Jun. 2001.
[13] R. Schreier, J. Silva, J. Steensgaard, G. C. Temes, “Design-Oriened Estimation of Thermal Noise in Switched-Capacitor Circuits,” IEEE Tran. Circuits and syst. I, vol. 52, no. 11, pp. 2358-2368, Nov. 2005.
[14] K. S. Kim, J. Kim, and S. H. Cho, “Nth-order multi-bit ΣΔ ADC using SAR quantizer,” Electron. Lett., vol. 46, no. 19, pp. 1315-1316, Sep. 2010.
[15] P. Harpe, Y. Zhang, G. Dolmans, K. Philips, H. D. Groot, “A 7-to-10b 0-to 4MS/s Flexible SAR ADC with 6.5-to-16fJ/conversion-step,” ISSCC Dig. Tech. Papers, pp. 472-473, Feb., 2012.
[16] L. Bos, G. Vandersteen, Y. Rolain, “Multirate Cascasded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS,” IEEE J. Solid-State Circuits, vol. 45, pp. 1198-1208, Jun. 2010
[17] J. G. Kauffman, P. Witte, J. Becker, M. Ortmanns, “An 8mW 50MS/s CT ΔΣ Modulator with 81dB SFDR and Digital Background DAC Linearization,” IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp. 472–473.
[19] N. Maghari, U. K. Moon, “A Third-Order DT ΔΣ Modulator Using Noise-Shaped Bidirectional Single-Slope Quantizer,” IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp. 474–475.
[20] M. Furuta, M. Nozawa, and T. Itakura, “A 0.06mm2 8.9b ENOB 40MS/s pipelined SAR ADC in 65 nm CMOS,” IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 382–383.
[21] M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamoto, “A 10b 50MS/s 820W SAR ADC with on-chip digital calibration,” IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 384–385.
[22] C. C. Liu, S. J. Chang, G. Y. Huang, Y. Z. Lin and C. M. Huang, “A 1V 11fJ/Conversion-Step 10bit 10MS/ Asynchronous SAR ADC in 0.18μm CMOS,” IEEE Symp, on VLSI Circuits Dig. Tech Papers, Jun. 2010, pp. 241-242.
[23] M. C. Huang, S. I. Liu, “A fully differential comparator based switched-capacitor ΔΣ modulator,” IEEE Tran. Circuits and syst. II, vol. 56, no. 5, pp. 369-373, May. 2009.