本論文中實現一技術來改善D類放大器中的輸出級失真，數位輸入D類放大器通常使用開迴路的架構，因此當以較大的輸出功率驅動負載時總諧波失真加雜訊會受到輸出級失真限制。工作週期補償技術提供局部補償改善輸出級失真，透過迴圈濾波器產生的控制訊號來控制輸入脈寬編碼訊號的工作週期，補償因總諧波失真導致的工作週期誤差。迴圈濾波器的高迴圈增益配合雜訊移頻的機制抑制頻寬內的失真，因而改善D類放大器的諧波失真表現。
本作品實現於TSMC 0.18微米製程，晶片面積為1.7毫米平方。驗證結果顯示在385千赫茲的切換頻率及8歐姆的負載下，此技術將最低諧波失真由原本的-82dB改善至-96dB，因本技術所增加的靜態電流為340微安培。與現有技術的數位輸入D類放大器相比，本作品有相當的諧波失真加雜訊及靜態電流消耗。

In this thesis, a technique to improve power stage distortion of Class-D amplifiers is implemented. Digital-input Class-D amplifiers usually use open-loop architecture therefore THD+N is limited by power-stage distortion when driving load with large output power. Duty cycle compensation technique provides local compensation for power-stage distortions. The technique controls the duty cycle of input PWM signal with control voltage generated by loop filter to compensate the duty cycle error caused by power stage distortion. The high loop gain of loop filter suppresses the in-band distortion with noise-shaping mechanism thus improving the THD of Class-D amplifiers.
This work is implemented in 0.18um process with 1.7mm2 chip area. Simulation result shows that the minimum THD is improved from -82dB to -96dB with the technique while driving an 8Ω load at 384kHz switching frequency. The quiescent current increase with the technique is 340μA. Compared with other state-of-the-art digital-input Class-D amplifiers, this work has comparable THD+N and quiescent current consumption.

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