本晶片是針對以電池作為系統電源之電容感測器來設計的讀出電路。本系統必需是低功率的以符合可攜式的要求；因著應用於麥克風，也必需注意線性度的考量，使放大後的訊號保持該有的音質。高線性度的電路通常需要高的驅動電壓，同時也消耗較多的功率，對於一個晶片工程師，取得這兩者之間的平衡的確是一個難題，尤其是在低電壓的情形下。本次提出的電路系統架構運用回授放大器來放大訊號，並將直流準位轉移器及倍壓器設計在晶片中及一些電路技巧來改善低電壓環境 (1.4V) 下對線性度的衝擊。本電路系統也藉連接前兩級放大器而等效出一個二階高通濾波器，這是本電路系統用以補償因回授放大器所造成較大功率消耗之缺點的技巧。這個晶片是用台灣積體電路製造公司(TSMC) 0.35微米互補金氧式半導體製成技術實現。而HSPICE模擬結果顯示第三諧波失真比為58dB、系統增益為5500，及功率消耗為222μW。

This work is designed for capacitive sensor in battery operation. For the portable requirement, the system must be low power; for the acoustic signal processing in microphone, linearity is another important issue to keep the quality in a compatible level. High linearity often costs larger over-drive voltage and consumes much power. It is hard to get a balance between them, especially in low voltage design. The proposed architecture utilizes feedback amplifier to manifest signal, and integrates level shifter and voltage doubler on chip with some techniques to reduce the impact on low linearity under the 1.4V supply voltage. The proposed system also creates a high-pass filter by cascades the first two amplifiers of system. It is the key point to compensate the disadvantage of larger power consumption caused by the feedback amplifier. This work is fabricated with TSMC 0.35um CMOS technology. The HSPICE simulation shows the third order harmonic distortion ratio (HD3) 58dB, whole system gain 5500, and power consumption 222μW.

[1] A. P. Chandran, K. Najafi, and K. D. Wise. “A new DC baseline stabilization scheme for neural recording microprobes,” in Proc. IEEE BMES/EMBS Conf., pp. 386,1999.
[2] C. Yoo; Seung-Wook Lee; W. Kim. “A ±1.5-V, 4-MHz CMOS continuous-time filter with a single-integrator based tuning,” JSSC, Vol. 33, No. 1, pp. 18 – 27, Jan. 1998.
[3] Carvajal, R.G.; Ramirez-Angulo, J.; Lopez-Martin, A.J.; Torralba, A.; Galan, J.A.G.; Carlosena, A.; Chavero, F.M. “The flipped voltage follower: a useful cell for low-voltage low-power circuit design,” TCASI, Vol. 52, Issue 7, pp. 1276 – 1291, July 2005.
[4] Chong-Gun Yu, R. L. Geiger. “An Automatic Offset Compensation Scheme with Ping-Pong Control for CMOS Operational Amplifiers,” JSSC Vol. 29, No. 5, pp.601 – 610, May 1994.
[5] D. A. Johns and K. Martin. ”Analog Integrated Circuit Design,” Wiley, New York, pp. 398, 1997.
[6] D. Dzahini, H. Ghazlane. “Auto-zero stabilized CMOS amplifiers for very low voltage or current offset,” Nuclear Science Symposium Conference IEEE, Vol. 1, pp.6 – 10, Oct. 2003.
[7] D. W. H. Calder. “ Audio frequency gyrator filters for and integrated radio paging receiver,” in Proc. IEE Conf. Mobile Radio Syst. Tech., pp. 21-26, 1984.
[8] Dragan Maksimovie and Sandeep Dhar. “Switched-capacitor DC-DC converters for low-power on-chip applications,” PESC 99, Vol. 1, pp. 54 – 59, July 1999.
[9] Duisters, T.A.F.; Dijkmans, E.C. “A -90-dB THD rail-to-rail input opamp using a new local charge pump in CMOS,” JSSC, Vol. 33, Issue 7, pp. 947 – 955, July 1998.
[10] Favrat P., Deval P., Declercq M.J. ”A high-efficiency CMOS voltage doubler,” JSSC, Vol. 33, No. 3, pp. 410-416, March 1998.
[11] Finvers, I.G.; Haslett, J.W.; Trofimenkoff, F.N. ”A high temperature precision amplifier,” JSSC, Vol. 30, Issue 2, pp. 120 – 128, Feb 1995.
[12] Harrison, R.R.; Charles, C. ” A low-power low-noise CMOS amplifier for neural recording applications,” JSSC, Vol. 38, Issue 6, pp. 958 – 965, June 2003.
[13] Hernes, B.; Sansen, W. “Distortion in single-, two- and three-stage amplifiers,” TCASI, Vol. 52, Issue 5, pp. 846 – 856, May 2005.
[14] Horowitz, P.; Hill, W. “The art of electronics,” Cambridge university press, New York, pp. 428-449, 1994.
[15] http://www.mathwork.com (MATLAB R-14, version 7)
[16] Jimmin Chang; Abidi, A.A.; Viswanathan, C.R. ”Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures,” EDTS, Vol. 41, Issue 11, pp. 1965 - 1971, Nov. 1994.
[17] Joseph J. Carr, John M. Brown. “Introduction to biomedical equipment technology,” Prentice Hall, New Jersey, pp. 77-79, 2001.
[18] Kwan, T.; Martin, K. ” An adaptive analog continuous-time CMOS biquadratic filter,” JSSC, Vol. 26, Issue 6, pp. 859 – 867, June 1991.
[19] M. Koyama, T.Arai, H. Tanimoto, and Y. Yoshida. “A 2.5-V Active Low-Pass Filter Using All npn Gilbert Cells with a 1-Vp-p Linear Input Range,” JSSC, Vol. 28, pp.1246-1253, Dec. 1993.
[20] Nakagome, Y.; Itoh, K.; Takeuchi, K.; Kume, E.; Tanaka, H.; Isoda, M.; Musha, T.; Kaga, T.; Kisu, T.; Nishida, T.; Kawamoto, Y.; Aoki, M. ”Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM,” JSSC, Vol. 26, Issue 7, pp. 1003 – 1010, July 1991.
[21] Phillip E. Allen, Douglas R. Holberg. “CMOS Analog Circuit Design,” Oxford, New York, pp. 393, 2002.
[22] Serdijn, W.A.; van der Woerd, A.C.; Davidse, J.; van Roermund, A.H.M. ” A low-voltage low-power fully-integratable front-end for hearing instruments,” TCASI, Vol. 42, Issue 11, pp. 920 – 932, Nov. 1995.
[23] Veeravalli, A.; Sanchez-Sinencio, E.; Silva-Martinez, J. ” Transconductance amplifier structures with very small transconductances: a comparative design approach,” JSSC, Vol. 37, Issue 6, pp. 770 – 775, June 2002.
[24] Wong, S.L. “Novel drain-biased transconductance building blocks for continuous-time filter applications,” Electron. Lett. Vol. 25, Issue 2, pp. 100 – 101, Jan. 1989.
[25] Woo, Barry. B. “Digitally programmable gain amplifiers with arbitrary range of integer values,” proc. IEE, Vol. 68, No. 7, pp. 934 – 936, July 1980.