時間數位轉換器(Time-to-digital converters)非常類似於類比數位轉換器，然而不同之處在於時間數位轉換器並不是轉換電流或是電壓，而是將兩個正緣訊號所組成的時間區間轉換成數位訊號。原本時間數位轉換器只應用於高能物理實驗，之後時間數位轉換器也被廣泛的應用於雷射測距儀(Laser range finder)、正電子發射計算機斷層掃描(Positron emission tomography)等儀器...。隨著近幾年的發展，TDCs逐漸應用於一些混和訊號的電路設計像是全數位鎖相迴路/(All-digital PLL/DLLs)，並作為時間量化器或是相位偵測器(Phase detector)來影響整個電路效能。為了達到更高的效能要求，一個有更快轉換速率以及高解析度(Resolution)的TDC是必須的。
本論文提出有高解析度以及取樣速率的時間數位轉換器，為了改進解析度以及轉換效率提出了具備多取樣功能的時間放大器並應用到時間數位轉換器並達到4.7ps解析度以及400Ms/s的轉換速率，並會把全部的電路設計以台積電40奈米製程實作下線，並保留部分重要接線以測試各區塊的正確性。

Time-to-digital converters (TDCs) are very similar to analog-to-digital converters (ADCs). The difference is that the TDC does not convert the current or voltage, but convert the measured time interval to digital signals. The original TDC is only used in high-energy physics experiments. Now TDCs are widely used in laser range finders, positron emission tomography and other instruments. With the development of recent years, TDCs are gradually applied to some mixed-signal circuit design such as a time quantizer or a phase detector in all-digital PLL / DLL. As one of the major cores, TDCs affect the overall circuit performance. In order to achieve higher performance requirements, TDCs need to have faster conversion rate and higher resolution.
In this thesis, a TDC with high resolution and sampling rate is presented. For improving resolution and conversion rate, a time amplifier with multi-sampling applies to this time-to-digital converter and achieves 4.7ps resolution and 400Ms/s conversion rate. The whole circuit was taped out using TSMC 40nm process to validate the proposed method.

[1] S. Henzler, Time-to-Digital Converters (Springer Series in Advanced Microelectronics), vol. 29, The Netherlands: Springer, 2010
[2] S. Naraghi, Time-Based Analog To Digital Converters. Ph.D. thesis, The University of Michigan, 2009.
[3] Manuel José dos Reis Gaspar Seabra Mota, “Design and Characterization of CMOS High-Resolution TDCs,” Ph.D. dissertation, Dept. Elect. Eng., Lisbon Technical Univ., Lisbon, Portugal , 2000
[4] K. Kim, W. Yu, and S. Cho, “A 9 bit, 1.12 ps resolution 2.5 b/stage pipelined time-to-digital converter in 65 nm CMOS using time-register,” IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 1009–1017, Apr. 2014.
[5] T. Oh, H. Venkatram, and U. K.Moon, “A time-based pipelined ADC using both voltage and time domain information,” IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 961–971, 2014.
[6] Y. Wu, M. Shahmohammadi, Y. Chen, P. Lu, and R. B.Staszewski, “A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH  ΔΣ TDC for low in-band phase noise,” in Proc. Eur. Solid-State Circuits Conf., vol. 2016–October, pp. 209–212, 2016.
[7] P. Lu, A. Liscidini, and P. Andreani, “A 2-D GRO Vernier time-to-digital converter with large input range and small latency,” Analog Integr. Circuits Signal Process., vol. 76, no. 2, pp. 195–206, Jun. 2013.
[8] J. Yu and F. F. Dai, “A 3-dimensional Vernier ring time-to-digital converter in 0.13 um CMOS,” in Proc. IEEE Custom Integrated Circuits Conference, 2010, pp. 1–4.
[9] Z. Cheng, M. J.Deen, and H. Peng, “A Low-Power Gateable Vernier Ring Oscillator Time-to-Digital Converter for Biomedical Imaging Applications,” IEEE Trans. Biomed. Circuits Syst., vol. 10, no. 2, pp. 445–454, 2016.
[10] M. Lee and A. A.Abidi, “A 9 b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 769–777, 2008.
[11] J. Kim, T. K.Jang, Y. G.Yoon, and S. Cho, “Analysis and design of voltage-controlled oscillator based analog-to-digital converter,” IEEE Trans. Circuits Syst. I Regul. Pap., vol. 57, no. 1, pp. 18–30, 2010.
[12] B. Kim, H. Kim, and C. H. Kim, “An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier,”in Proc. Cust. Integr. Circuits Conf., vol. 2015–Novem, pp. 6–9, 2015.
[13] H. Chung, H. Ishikuro, and T.Kuroda, “A 10-bit 80-MS/s decision-select successive approximation TDC in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 5, pp. 1232–1241, 2012.
[14] S. Liu and Y. Zheng, “A low-power and highly linear 14-bit parallel sampling TDC with power gating and DEM in 65-nm CMOS,” IEEE Trans. Very Large Scale Integr. Syst., vol. 24, no. 3, pp. 1083–1091, 2016.
[15] Y. H.Seo, J. S. Kim, H. J. Park, and J. Y. Sim, “A 1.25 ps resolution 8b cyclic TDC in 0.13 μ CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 736–743, 2012.
[16] Y. H. Seo, J. S. Kim, H. J. Park, and J. Y. Sim, “A 0.63 ps resolution, 11 b pipeline TDC in 0.13 m CMOS,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2011, pp. 152–153.
[17] S. J. Kim, W. Kim, M. Song, J. Kim, T. Kim, and H. Park, “A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16 spatial redundancy in 14nm FinFET technology,” in Proc. IEEE Int. Solid-State Circuits Conf., vol. 58, pp. 280–281, 2015.
[18] B. Nikolić, V. G. Oklobdžija, V. Stojanovič, W. Jia, J. K. S.Chiu, and M. M. T. Leung, “Improved sense-amplifier-based flip-flop: design and measurements,” IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876–884, 2000.
[19] M. H. Sheu, J. F. Lin, Y. T. Hwang, and C. S. Wong, “Single-ended structure sense-amplifier-based flip-flop for low-power systems,” Electron. Lett., vol. 51, no. 1, pp. 20–21, 2015.
[20] METERING & SMART ENERGY, “Smart meters: Can energy harvesting cut maintenance time,” 2016, Available: https://www.metering.com/features/smart-meters-can-energy-harvesting-cut-maintenance-time/
[21] F. Villa, B. Markovic, S. Bellosai, D. Bronzi, A. Tosi, F. Zappa, S. Tisa et al, “SPAD smart pixel for time-of-flight and time-correlated single-photon counting measurements,” IEEE Photonics Journal, Vol. 4,No. 3, pp. 795-804, June.