本論文提出了一個低面積、高效率的硬體架構來解碼H.264/AVC標準中的殘值。這個架構包含了CAVLC解碼器、反量化器、反轉換器。在硬體設計上，因為這些元件的解碼速度不同，在元件之間的介面必須很小心的設計來緩衝它們之間的資料傳輸。為了有效的實現 CAVLC解碼器和反量化器之間的介面，我們首先分析了在H.264/AVC標準中的解碼流程。在適當的安排CAVLC解碼器和反量化器的解碼流程後，所提出的架構只需要一個反量化器，而且我們更進一步將它整合到CAVLC解碼器中來減少緩衝器的面積。另外一方面，我們也提出一個包含4 4整數反轉換、4 4 Hadamard反轉換以及2 2 Hadamard反轉換的彈性二維轉換架構。在模擬之後顯示，所提出的全部架構其電路使用的面積是14.1 k，而最大的操作頻率可以到達130 MHz。這樣的處理速度可以達到即時處理4:2:0的格式、每秒30張、畫面解析度為4VGA大小的影像。

A low cost and efficient architecture for decoding the residual data in the H.264/AVC is proposed in this thesis. The required components consist of CAVLC decoder, inverse quantizer, and inverse transform. Since the decoding speed of these components is varied, the interface should be designed carefully to buffer the data among them. To efficiently realize the interface of the CAVLC decoder and inverse quantizer, the residual decoding procedure in the H.264/AVC is first analyzed. After the proper arrangement of the CAVLC decoding and inverse quantization procedures, the proposed architecture requires only one inverse quantizer which is further combined into the CAVLC decoder to reduce the buffer size. Moreover, the flexible 2-D multi-transform architecture which including the 4 4 inverse integer transform, 4 4 inverse Hadamard transform, and 2 2 inverse Hadamard transform is also proposed. Simulation results show that the total implemented gate counts is 14.1 k and the maximum operation frequency is 130 MHz in the proposed design. It can support the real-time requirement for the 4VGA @30 fps video resolution in 4:2:0 formats.

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