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研究生： 林進富
Lin, Jin-Fu
論文名稱： 低功率導管式和循環式類比至數位轉換器之設計與測試
Design and Test of Low Power Pipelined/Cyclic Analog-to-Digital Converters
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 博士
Doctor
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2010
畢業學年度： 98
語文別： 英文
論文頁數： 175
中文關鍵詞： 具關連性重複取樣技術 、導管式類比至數位轉換器 、類差動放大器 、轉換碼式線性度測試方法
外文關鍵詞： correlated double sampling, pipelined, cyclic, ADC
相關次數： 點閱：88  下載：12 
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    • 本論文提出數個應用於導管式和循環式類比至數位轉換器之電路設計與測試技術，其分別具有低功率消耗以及有效減少測試時間和偵錯困難度的優點。本論文所提出之電路設計與測試技術簡述如下：
    (1) 電路設計技術
    本論文提出兩種新型具關連性重複取樣技術：分時多工式和分裂電容式具關連性重複取樣技術。此兩種技術可有效克服傳統具關連性重複取樣技術的兩倍電容負載和需要額外的時脈相位等問題，並具有較低功率消耗的優點。除此之外，本論文亦提出一直接耦合式具關連性電壓位移技術，該技術可大幅加快傳統具關連性電壓位移技巧的操作速度和加強校正增益誤差的能力。
    在本論文中，我們實現兩個低功率導管式類比至數位轉換器以驗證本論文所提出之兩種具關連性重複取樣技術。第一個設計採用分時多工式具關連性重複取樣技術，在0.13微米互補式金氧半電晶體製程下，實現一個9位元，100百萬次/秒的複合導管循序漸近式之類比至數位轉換器。藉由所提出之分時多工式具關連性重複取樣技術，此設計無需取樣與維持電路，並且可以僅使用低增益放大器來實現高精確度的導管式類比至數位轉換器，藉此有效降低類比至數位轉換器的消耗功率。除此之外，在電路架構上，我們使用分時多工式循序漸近式類比至數位轉換器來實現後級管路級，以更進一步降低整體轉換器的功率消耗。
    第二個設計採用分裂電容式具關連性重複取樣技術，在0.18微米互補式金氧半電晶體製程下，實現一個10位元，60百萬次/秒的導管式類比至數位轉換器。分裂電容式具關連性重複取樣技術可更進一步避免先前分時多工式具關連性重複取樣技術的兩倍電容負載問題，藉此更提高類比至數位轉換器的轉換效率。另外，在此設計中，我們提出一個新型高功率效率AB式類差動放大器，該放大器相較於傳統全差動架構具有更低的功率消耗的優點，但此電路對於共模準位漂移極為敏感，因此，我們提出一個名為積分式共模穩定電路以克服此問題。
    除了導管式類比至數位轉換器的電路技術開發，本論文亦針對衛星影像感測系統的應用，開發新型電路技術以實現一個10位元，14百萬次/秒之低功率循環式類比至數位轉換器。在此設計中，我們提出一運算放大器和電容共用技巧，用以降低循環式類比至數位轉換器的功率消耗，並且採用高功率效率、寬頻的增益提升運算放大器架構來更進一步降低電路的功率消耗。
    (2) 測試技術
    為了有效減少導管式和循環式類比至數位轉換器的測試時間，本論文提出一個轉換碼式線性度測試方法。此方法藉由詳細分析管路級的非理想行為，歸納出其特定線性度錯誤的表現行為，再利用導管式和循環式類比至數位轉換器在架構上的規則性，推演出可以只測試少數特定的轉換碼即可得到準確的導管式和循環式類比至數位轉換器的線性度測試結果，以減少測試時間。為了能夠準確偵測出具代表性的轉換碼，本論文提出一個簡單的測試輔助數位電路，使所提出的測試方法能更廣泛地應用於具有比較器誤差校正的導管式和循環式類比至數位轉換器。我們利用台積電0.35微米互補式金氧半電晶體製程實現一12位元，25百萬次/秒的導管式類比至數位轉換器來驗證所提出之測試方法。實驗結果顯示，本論文所提出之測試方法只需傳統直方圖式線性度測試方法9.3%的測試時間。
    此外，本論文提出一數位式輔助偵錯方法，透過將每級待測電路適當地加以重組以分離出各種錯誤效應，藉此避免各種錯誤效應互相蒙蔽的問題，達到導管式和循環式類比至數位轉換器的偵錯目的。此方法只需要簡單的數位電路來產生測試訊號即可有效偵測出電路中的運算放大器實際增益、電容不匹配、待測管路級的輸出偏移電壓和比較器輸入偏移電壓。額外加入的重組開關只會增加少許電路面積，並且不會對電路原本的特性造成影響。針對所提出之錯誤偵測技術，本論文藉由蒙地卡羅模擬來驗證此方法的有效性和可靠度。

    This dissertation proposes several circuit design and test techniques for pipelined/cyclic analog-to-digital converters (ADCs). The proposed design and test techniques have the advantages of low power consumption, short test time and less difficulty in debugging. The proposed techniques can be categorized and summarized as follows:
    1) Circuit Design Techniques
    In this dissertation, two correlated double sampling (CDS) techniques, i.e. time-interleaved CDS and split-capacitor CDS, are proposed to overcome the problems of double capacitive loading and one extra clock phase in prior CDS techniques. In addition, a direct-coupled correlated level shifting (CLS) technique is proposed to enhance the operating speed and gain-enhancement ability of prior CLS techniques.
    Two pipelined ADCs are implemented to verify the proposed CDS techniques. First, a 9-bit, 100-MS/s hybrid pipelined-SA ADC with the proposed time-interleaved CDS is implemented in the 0.13 um triple-well 1P8M CMOS process. With the help of the time-interleaved CDS, low-gain amplifiers and an SHA-less architecture can be used to effectively reduce power consumption of a pipelined ADC. In addition, the back-end pipelined stages are replaced by a low-power time-interleaved successive approximation (SA) ADC to further reduce the power consumption.
    Second, a 10-bit 60-MS/s pipelined ADC with the proposed split-capacitor CDS is implemented in a pure digital 0.18um 1P5M CMOS process. The double loading problem of conventional CDS techniques can be overcome by manipulating the proposed split-capacitor CDS. Low-gain amplifiers and an SHA-less architecture are also used in this design. Moreover, a power-efficient class-AB pseudo-differential op-amp and its corresponding integrator-based common mode stabilization (IB-CMS) method are developed to further reduce the power consumption of the ADC.
    In addition to the two pipelined ADCs with the proposed CDS techniques, a low-power 10-bit, 14-MS/s cyclic analog-to-digital converter (ADC) is developed in the TSMC 0.18-um triple-well 1P3M CMOS image sensor (CIS) process for a satellite CMOS image sensor application. Capacitor and op-amp reuse techniques are proposed to reduce the power consumption and the occupied silicon area. Moreover, a power-efficient wide-bandwidth telescopic cascoded gain boosting amplifier with capacitive level shifters is adopted to further decrease its power consumption.
    2) Circuit Testing Techniques
    A transition-code based method is proposed to reduce the linearity testing time of pipelined and cyclic ADCs. By employing specific architecture-dependent rules, only a few specific transition codes need to be measured to accomplish the linearity test of a pipelined ADC. In addition, a simple digital Design-for-Test (DfT) circuit is proposed to detect representative transition codes of each pipelined stage. With the DfT circuit, the proposed method can be extensively applied for pipelined ADCs with digital error correction (DEC) technique used to correct offset errors. Experimental results show that the proposed method can achieve high test accuracy for a 12-bit, 25-MS/s pipelined ADC by measuring only 9.3% of the total samples in a conventional histogram based method.
    To accurately diagnose error sources and significantly reduce debugging effort in pipelined ADCs, a digital design-for-diagnosis method is also proposed in this dissertation. The stage under test (SUT) is configured to separate each error effect. Stages after the SUT are properly configured as a cyclic ADC to digitize the residual output voltage of the SUT. Critical circuit parameters, such as op-amp gain, capacitor mismatch, stage offset, and comparator offset, are identified in the digital domain. Accurate analog test stimuli are not necessary for the proposed design-for-diagnosis scheme. A simple digital decoder is employed to generate the test signals. The DfT circuitry induces minor area overhead and negligible performance degradation of the circuit under test. Monte Carlo simulations are performed to demonstrate the effectiveness and reliability of the proposed method.

    List of Tables XII List of Figures XIII Chapter 1 Introduction 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 8 Chapter 2 Low-Power Pipelined ADCs without High-Gain Op-Amp 10 2.1 PROPOSED CDS TECHNIQUES 11 2.1.1 Conventional MDAC Architecture 11 2.1.2 MDAC Architectures with Prior CDS Techniques 13 2.1.2.1 Conventional CDS Technique [42] 13 2.1.2.2 Time-Shifted CDS Technique [43] 15 2.1.3 Proposed SHA with Time-Interleaved CDS Technique 18 2.1.4 Proposed MDAC with Time-Interleaved CDS Technique 20 2.1.4.1 Circuit Operation 20 2.1.4.2 Design Considerations of Channel Mismatches 21 2.1.5 Proposed MDAC with Split-Capacitor CDS Technique 23 2.2 A 9-BIT, 100-MS/S LOW-POWER HYBRID PIPELINED-SA ADC WITH TIME-INTERLEAVED CDS TECHNIQUE 26 2.2.1 Architecture 26 2.2.2 Design Considerations for SHA-less Architecture 27 2.2.3 Power-Efficient Back-End Pipelined Stage Design 29 2.2.3.1 Power-Scaling Limitations in Conventional Pipelined ADC 29 2.2.3.2 Resolution Selection of Time-Interleaved SA ADC 30 2.2.4 Circuit Implementations and Design Considerations for Back-End SA ADC 35 2.2.5 Low-Power and Low-Gain Amplifier 38 2.2.6 Experimental Results 40 2.3 A 10-BIT, 60-MS/S LOW-POWER PIPELINED ADC WITH SPLIT-CAPACITOR CDS TECHNIQUE 45 2.3.1 Architecture 45 2.3.2 Design Issues of SHA-Less Architecture 46 2.3.3 Pseudo-Differential Op-Amp Architecture 49 2.3.4 Measurement Results 52 2.4 PROPOSED CORRELATED LEVEL SHIFTING (CLS) TECHNIQUE 56 2.4.1 Introduction 56 2.4.2 Conventional CLS Technique [48] 57 2.4.3 Prior Cross-Coupled CLS Technique [105] 59 2.4.4 Proposed Direct-Coupled CLS Technique 60 2.4.5 Simulation Results 62 2.5 SUMMARY 64 Chapter 3 Low-Power Cyclic ADC for CMOS Image Application 66 3.1 INTRODUCTION 66 3.2 ARCHITECTURE OF PROPOSED CYCLIC ADC 69 3.2.1 Conventional Architecture 69 3.2.2 Review of Previous Loading-Free Technique [30] 69 3.2.3 MDAC Architecture 72 3.2.4 Proposed Capacitor Reuse Technique 74 3.2.5 Circuit Diagram 76 3.3 CIRCUIT IMPLEMENTATIONS 79 3.3.1 Programmable Gain Amplifier (PGA) 79 3.3.2 Operational Amplifier 81 3.3.3 Sub-ADC 82 3.4 EXPERIMENTAL RESULTS 83 3.5 SUMMARY 91 Chapter 4 Transition-Code Based Linearity Test Method 93 4.1 INTRODUCTION 93 4.2 ERROR MECHANISM OF PIPELINED ADCS 95 4.3 TESTING CONCEPT OF PROPOSED TRANSITION-CODE BASED METHOD 99 4.3.1 Error Effects in the First Pipelined Stage 100 4.3.2 Error Effects in Multiple Pipelined Stages 101 4.4 TRANSITION CODE DETECTION 102 4.4.1 Offset Effect in the Proposed Method 103 4.4.2 Proposed Design-for-Test Circuit 105 4.5 TEST PROCEDURE 107 4.5.1 Estimate ADC Offset 108 4.5.2 Detect Transition Codes 109 4.5.3 Test Transition Codes 111 4.5.4 Fill Results in Un-selected Transition Codes 113 4.6 EXPERIMENTAL RESULTS 114 4.6.1 Simulation Results 115 4.6.2 Measurement Results 119 4.7 SUMMARY 127 Chapter 5 Digital Design-for-Diagnosis Method for Pipelined/Cyclic ADCs 128 5.1 INTRODUCTION 128 5.2 ERROR MECHANISM OF PIPELINED ADCS 129 5.3 IDENTIFYING GAIN ERROR SOURCES 130 5.3.1 Concept 130 5.3.2 Op-Amp Gain 132 5.3.3 Capacitor Mismatch 133 5.3.4 Considerations of Test Signal 134 5.3.5 Back-End ADC 137 5.4 IDENTIFYING OFFSET ERROR SOURCES 139 5.4.1 Input Referred Noise of Stage under Test 139 5.4.2 Comparator Offset 140 5.6 IDENTIFICATION ACCURACY 142 5.5.1 IDENTIFICATION ABILITY 142 5.5.2 IDENTIFICATION ERROR 143 5.6 CIRCUIT IMPLEMENTATION 145 5.6.1 Design-for-Diagnosis Pipelined Stage 146 5.6.2 Test Signal Generator 146 5.6.3 Architecture of Proposed Diagnosis Method 147 5.7 SIMULATION RESULTS 148 5.8 SUMMARY 152 Chapter 6 Conclusions and Future Work 153 6.1 CONCLUSIONS 153 6.2 FUTURE WORK 156 Reference 158

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